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US 7,679,129 B1Granted
System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device
AssigneesSpansion LLC, Globalfoundries Inc.
InventorsAngela T. Hui, Unsoon Kim, Hiroyuki Kinoshita, Kuo-Tung Chang
Life of this patent
Estimating the term…
Abstract
A memory device includes a substrate and a first dielectric layer formed over the substrate. At least two charge storage elements are formed over the first dielectric layer. The substrate and the first dielectric layer include a shallow trench filled with an oxide material. The oxide material formed in a center portion of the shallow trench is removed to provide a region with a substantially rectangular cross-section.
Claims9
A memory device, comprising:
- a semiconductor substrate;
- a first dielectric layer formed over the semiconductor substrate;
- at least two charge storage elements formed over the first dielectric layer,
- where the semiconductor substrate and the first dielectric layer include a shallow trench filled with an oxide material, the shallow trench having opposing sidewalls, and
- where the oxide material, formed in a center portion of the shallow trench below an upper surface of the semiconductor substrate and between the opposing sidewalls, is removed to provide a region with a substantially rectangular cross-section, and where the oxide material is removed, so that a top surface of the oxide material is in contact with the at least two charge storage elements and does not extend past a top surface of the first dielectric layer;
- and
- an intergate dielectric formed over at least one of the at least two charge storage elements, the intergate dielectric extending into the center portion of the shallow trench.
4 more elements
A non-volatile memory array, comprising:
- a plurality of memory cells, each including a first dielectric layer formed over a semiconductor substrate, and a charge storage element formed over the first dielectric layer;
- a plurality of isolation regions separating the plurality of memory cells, each of the isolation regions including a trench formed in the semiconductor substrate and including opposing sidewalls, and an oxide formed in the trench, where the oxide located in a center portion of an upper portion of the trench below an upper surface of the semiconductor substrate and between the opposing sidewalls is removed, so that a top surface of the oxide is in contact with the charge storage element and does not extend past a top surface of the first dielectric layer;
- and
- where each of the plurality of memory cells further comprises:
- an intergate dielectric formed over the charge storage element, the intergate dielectric extending into the center portion of the upper portion of the trench between the sidewalls;
- and
- a control gate formed over a portion of the intergate dielectric.
4 more elements
Dependencies are inferred from the claim text.