A semiconductor device, comprising:
- a semiconductor substrate including a memory cell region and a peripheral circuit region, wherein the memory cell region has a plurality of first element regions and an element isolation region isolating the first element regions from each other, and the peripheral circuit region has a second element region;
- a shallow trench isolation located in the element isolation region including a first lower portion embedded in the semiconductor substrate and a first upper portion projecting from a surface of the semiconductor substrate, the first upper portion including a pair of first side surfaces and a first upper surface;
- a first gate insulating film located on the semiconductor substrate in the first element regions;
- a second gate insulating film located on the semiconductor substrate in the second element region;
- a first floating gate electrode located on the first gate insulating film, including a second lower portion having a second side surface facing to one of the first side surfaces and a second upper portion located on the second lower portion, the second upper portion including a second upper surface and a third side surface flush with the second side surface;
- a second floating gate electrode located on the first gate insulating film, including a third lower portion having a fourth side surface facing to the other of the first side surfaces and a third upper portion located on the third lower portion, the third upper portion including a third upper surface and a fifth side surface flush with the fourth side surface;
- a first inter-gate insulating film located on the first upper surface of the shallow trench isolation, the second upper surface of the first floating gate electrode, the third upper surface of the second floating gate electrode, the third side surface of the first floating gate electrode and the fifth side surface of the second floating gate electrode;
- a control gate electrode located on the first inter-gate insulating film, including a fourth lower portion having a fourth upper surface, a fourth upper portion and a first etching stopper film located between the fourth lower and upper portions, the fourth lower portion being located above the first upper surface, the second upper surface and the third upper surface so that a space between the second and the third upper portions is buried with the fourth lower portion and so that the fourth upper surface of the fourth lower portion is flush throughout regions of the first floating gate electrode, the second floating gate electrode and the shallow trench isolation;
- a lower electrode located on the second gate insulating film, including a fifth upper surface having a height relative to a surface of the second gate insulating film, said height of the fifth upper surface being the same as a height of the second and third upper surfaces relative to a surface of the first gate insulating film;
- a second inter-gate insulating film located on the fifth upper surface of the lower electrode and having a thickness that is the same as a thickness of the first inter-gate insulating film;
- and
- an upper electrode located on the second inter-gate insulating film, including a fifth lower portion having a sixth upper surface, a fifth upper portion and a second etching stopper film located between the fifth lower and upper portions,
- wherein the sixth upper surface and the second etching stopper film have an interface therebetween, and the interface has a height relative to the surface of the second gate insulating film, said height being the same as a height of an interface between the fourth upper surface and the first etching stopper film relative to the surface of the first gate insulating film.