Semiconductor integrated test structures for electron beam inspection of semiconductor wafers

A semiconductor device, comprising:

• an integrated device array formed on a semiconductor substrate, wherein a portion of the integrated device array comprises a test structure region, wherein the test structure region comprises:
• adjacent first, second and third active regions, wherein the first active region comprises a first well region and a first diffusion region formed in the first well region, wherein the second active region comprises a second well region and a second diffusion region formed in the second well region, and wherein the third active region comprises a third well region and a third diffusion region formed in the third well region;
• wherein the first well region, third well region and second diffusion region are doped with a first conductivity type, and wherein the second well region and the first and third diffusion regions are doped with a second conductivity type opposite the first conductivity type;
• a conductive pattern formed on the first, second and third active regions, wherein a first portion of the conductive pattern is formed in contact with, and bridging, the first diffusion region and the second diffusion region, and wherein a second portion of the conductive pattern is formed in contact with, and bridging, the second diffusion region and the third diffusion region;
• and
• an isolation structure formed in the second diffusion region and electrically isolating the first and second portions of the conductive pattern.