Method of fabricating memory device
AssigneeHynix Semiconductor Inc.
InventorSe Hyun Kim
Life of this patent
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Abstract
Disclosed herein is a method of fabricating a memory device. The method includes forming an etch stop layer, bit lines, and a first hard mask pattern over a semiconductor substrate. A first SNC plug is formed between the bit lines, and an etch process is performed to reduce the height of the first hard mask pattern and the first SNC plug, to increase a top width of the first hard mask pattern, and to reduce a top width of the first SNC plug. The method also includes forming a second hard mask pattern on the first hard mask pattern, and forming a second SNC plug between the second hard mask patterns.
Claims18
A method of fabricating a memory device, the method comprising:
- forming landing plugs between gates on a semiconductor substrate;
- forming an etch stop layer, a first conductive layer, and a first hard mask layer over the semiconductor substrate;
- etching the first hard mask layer to form first hard mask patterns;
- performing a first etch process to form bit lines by etching the first conductive layer and the etch stop layer using the first hard mask patterns as an etch mask;
- forming a first spacer on sidewalls of the bit line;
- gap-filling a second conductive layer between the bit lines;
- forming a first storage node contact (SNC) plug between the bit lines by polishing the second conductive layer until the first hard mask patterns are exposed;
- performing a second etch process to reduce a height of the first hard mask patterns and the first SNC plug;
- forming the second hard mask layer over the first hard mask patterns and the first SNC plug;
- etching the second hard mask layer to form second hard mask patterns on the first hard mask patterns;
- and
- forming a second SNC plug between the second hard mask patterns.
A method of fabricating a memory device, the method comprising:
- forming an etch stop layer, bit lines, and first hard mask patterns over a semiconductor substrate;
- gap-filling a conductive layer between the bit lines;
- forming a first SNC plug between the bit lines by polishing the conductive layer until the first hard mask patterns are exposed;
- performing an etch process to reduce a height of the first hard mask patterns and the first SNC plug to increase a top width of the first hard mask patterns, and to reduce a top width of the first SNC plug;
- forming the second hard mask layer over the first hard mask patterns and the first SNC plug;
- etching the second hard mask layer to form second hard mask patterns on the first hard mask patterns;
- and
- forming a second SNC plug between the second hard mask patterns.
Dependencies are inferred from the claim text.