Spacer layer etch method providing enhanced microelectronic device performance

A method for forming a field effect transistor device comprising:

• providing a semiconductor substrate;
• forming upon the semiconductor substrate a gate dielectric layer in turn having formed thereupon a gate electrode;
• forming within the semiconductor substrate a lightly doped extension region while employing the gate electrode as a mask;
• forming conformally upon the gate electrode a conformal spacer layer;
• forming within the semiconductor substrate a source/drain region while employing the gate electrode and the conformal spacer layer as a mask;
• forming upon the conformal spacer layer an additional spacer material layer;
• anisotropically etching the additional spacer material layer to form an anisotropically etched shaped spacer material layer adjoining the conformal spacer layer and exposing in part the source/drain region and the gate electrode;
• isotropically etching the anisotropically etched shaped spacer material layer to further expose the source/drain region and the gate electrode, wherein at least part of an upper sidewall of the gate electrode is exposed;
• and
• forming upon the further exposed source/drain region and gate electrode a pair of silicide layers.

A method for forming a field effect transistor device comprising:

• providing a semiconductor substrate;
• forming upon the semiconductor substrate a gate dielectric layer in turn having formed thereupon a gate electrode;
• forming within the semiconductor substrate a lightly doped extension region while employing the gate electrode as a mask;
• forming conformally upon the gate electrode a multi-layer conformal spacer layer;
• forming within the semiconductor substrate a source/drain region while employing the gate electrode and the conformal spacer layer as a mask;
• forming upon the conformal spacer layer an additional spacer material layer;
• anisotropically etching the additional spacer material layer to form an anisotropically etched shaped spacer material layer adjoining the conformal spacer layer and exposing in part the source/drain region;
• isotropically etching the anisotropically etched shaped spacer material layer to further expose the source/drain region, wherein at least part of an upper sidewall of the gate electrode is exposed;
• and
• forming upon the further exposed source/drain region a silicide layer.