Antifuse one time programmable memory array and method of manufacture

A method for making a one time programmable (OTP) memory array, the method comprising:

• providing a silicon-on-insulator (SOI) wafer, the SOI wafer comprising a support substrate, a buried oxide layer over and in physical contact with the support substrate, and a monocrystalline silicon layer over and in physical contact with the buried oxide layer;
• forming a plurality of isolation trenches in the monocrystalline silicon layer of the SOI wafer and extending down to the buried oxide layer;
• filling the plurality of isolation trenches with an isolation material that is in physical contact with the buried oxide layer to form a plurality of isolation regions in the monocrystalline silicon layer of the SOI wafer, wherein regions of the monocrystalline silicon layer of the SOI wafer remaining between the plurality of isolation trenches define a plurality of bit lines of the OTP memory array;
• forming an anti-fuse dielectric layer over and directly contacting the plurality of bit lines and the plurality of isolation regions;
• and
• forming a plurality of word lines over and directly contacting the anti-fuse dielectric layer, wherein the plurality of word lines lie substantially perpendicular in reference to the plurality of bit lines and wherein a unit cell of the OTP memory array is defined at each crossing of a word line of the plurality of word lines over a bit line of the plurality of bit lines.

A method for making a one time programmable (OTP) memory array, comprising:

• providing a support substrate;
• forming a buried insulator layer over and in physical contact with the support substrate;
• forming a plurality of bit lines over and in physical contact with the buried insulator layer, wherein the plurality of bit lines are separated from each other by isolation regions in physical contact with the buried insulator layer;
• forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions;
• and
• forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer, wherein the plurality of word lines lie substantially perpendicular in reference to the plurality of bit lines and wherein a unit cell of the OTP memory array is defined at each crossing of a word line of the plurality of word lines over a bit line of the plurality of bit lines.