Electrostatic discharge protection structures with reduced latch-up risks
AssigneeSofics BVBA
InventorBenjamin Van Camp
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Abstract
The present invention provides an ESD protection circuitry in a semiconductor integrated circuit (IC) having protected circuitry to prevent false triggering of the ESD clamp. The circuitry includes an SCR as an ESD clamp having an anode adapted for coupling to a first voltage source, and a cathode adapted for coupling to a second voltage source. The circuitry also includes at least one noise current buffer (NCB) coupled between at least one of a first trigger tap of the SCR and the first voltage source such that the first trigger tap of the SCR is coupled to a power supply.
Claims17
An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, the ESD protection circuit comprising:
- a first voltage source of a protected circuit node of the IC;
- a silicon control rectifier (SCR) having an anode adapted for coupling to the first voltage source, and a cathode adapted for coupling to a second voltage source;
- and
- at least one noise current buffer (NCB) coupled between at least one of a first trigger tap of the SCR and the first voltage source, said at least one of the first trigger tap of the SCR is coupled to a third voltage source.
Dependencies are inferred from the claim text.