US 7,667,515 B1Granted

Time delay apparatus and method of using same

AssigneeHRL Laboratories, LLC

InventorsKen Elliott, Susan Morton, Mark Rodwell

Life of this patent

Estimating the term…

Loading patent…

Abstract

Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.

Claims15

Dependent claims

A time delay generator for variably delaying an input signal in accordance with a digital signal input, the time delay generator comprising:

(a) signal delaying means for outputting a delayed input signal by delaying the input signal a predetermined time period;
(b) a digital to analog converter, responsive to the digital signal input, for controlling current through a plurality of control signals;
and
(c) mixing means, responsive to the plurality of control signals, for generating a delayed output signal by mixing the delayed input signal and the input signal in proportion to the current through the plurality of control signals, respectively, wherein the signal delaying means provides a maximum delay within which the delayed output signal may lag behind the input signal and the maximum delay is independent of the current through the plurality of control signals, and
wherein a delay between the input signal and the delayed output signal is substantially linear with the digital signal input.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/156,266Filed 31 May 2008 · continuation
Priority: 25 Sep 2002
Granted: 23 Feb 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03K 17/603
The devices being bipolar transistors: with coupled emitters
H03K 5/131
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: digitally controlled
H03K 17/6264
With several inputs only combined with selecting means: using current steering means
H03K 2005/00065
Controlled by a digital setting: by current control, e.g. by parallel current control transistors