Latch structure and bit line sense amplifier structure including the same

A layout structure of a latch comprising:

• a semiconductor substrate;
• a first inverter formed on the semiconductor substrate, and including a first PMOS transistor and a first NMOS transistor;
• and
• a second inverter formed on the semiconductor substrate and coupled with the first inverter, and including a second PMOS transistor and a second NMOS transistor, the second inverter configured to receive an output signal of the first inverter, and output an input signal to the first inverter,
• wherein the first PMOS transistor includes a first PMOS active region in which is formed a source and a drain of the first PMOS transistor, and a first PMOS gate electrode formed on the first PMOS active region,
• the second PMOS transistor includes a second PMOS active region in which is formed a source and a drain of the second PMOS transistor, and a second PMOS gate electrode formed on the second PMOS active region,
• the first PMOS active region and the second PMOS active region are arranged adjacent to each other in a longitudinal direction, and the sources of the first and second PMOS transistors are connected to a first common source line, and
• the first PMOS gate electrode is symmetrical to the second PMOS gate electrode with respect to a first folding line between the first and second PMOS active regions.