Electrostatic discharge protection for a circuit capable of handling high input voltage
AssigneeSmartech Worldwide Limited
InventorKenneth Wai Ming Hung
Life of this patent
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Abstract
An electrostatic discharge protection circuit includes a first NMOS transistor and a second NMOS transistor cascode-connected between a high-voltage supply terminal (VDD) and an input pad (PAD), a third NMOS transistor and a fourth NMOS transistor cascode-connected between PAD and a low-voltage supply terminal (VSS), a first capacitor connected between VDD and a node VT that is connected to gate terminals of the second NMOS transistor and the third NMOS transistor, a second capacitor connected between the node VT and PAD, and a diode connected between VDD and the node VT.
Claims20
An electrostatic discharge protection circuit, comprising:
- a first NMOS transistor and a second NMOS transistor cascode-connected between a high-voltage supply terminal VDD and an input pad PAD;
- a third NMOS transistor and a fourth NMOS transistor cascode-connected between PAD and a low-voltage supply terminal VSS;
- a first capacitor connected between VDD and a node VT which is connected to gate terminals of the second NMOS transistor and the third NMOS transistor;
- a second capacitor connected between the node VT and PAD;
- and
- a diode connected between VDD and the node VT.
An electrostatic discharge protection circuit, comprising:
- a first NMOS transistor and a second NMOS transistor cascode-connected between a high-voltage supply terminal VDD and an input pad PAD;
- a third NMOS transistor and a fourth NMOS transistor cascode-connected between PAD and a low-voltage supply terminal VSS;
- a first capacitor connected between VDD and a node VT which is connected to gate terminals of the second NMOS transistor and the third NMOS transistor,
- a second capacitor connected between the node VT and PAD;
- a diode connected between VDD and the node VT;
- an inverter connected between the node VT and VSS, the inverter having an input node VI and an output node VB connected to gate terminals of the first NMOS transistor and the fourth NMOS transistor;
- a first resistor connected between the node VT and the node VI;
- a third capacitor connected between the node VI and VSS, wherein the first capacitor and the second capacitor define a capacitive-coupling time constant between VDD and PAD, wherein the first resistor and the third capacitor define an RC time constant between the node VT and the node VI, wherein the RC time constant is longer than the capacitive-coupling time constant;
- and
- a second resistor connected between VSS and the node VB.
Dependencies are inferred from the claim text.