Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void

A semiconductor device comprising:

• a semiconductor substrate having an upper trench and a lower trench to collectively define an active region, the lower trench having a substantially curved cross-sectional profile, the lower trench being in communication with the upper trench;
• and
• an isolation layer formed inside the upper trench and the lower trench of the semiconductor substrate, the isolation layer comprising:
• a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench;
• a second insulating layer overlying the first insulating layer and covering an inner wall of the lower trench;
• and
• a third insulating layer overlying the second insulating layer and extending from the upper trench to the lower trench to define a closed void inside the lower trench,
• wherein the upper trench has a first width at an upper portion and a second width at a lower portion, the first width being greater than the second width, and the lower trench has a third width corresponding to a maximum width of the lower trench, the third width being greater than the second width and less than the first width.