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US 7,622,757 B2Granted
Semiconductor device having multiple wiring layers
AssigneeKabushiki Kaisha Toshiba
InventorsKoichi Endo, Yasuto Sumi, Katsuyuki Adachi
Life of this patent
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Abstract
A semiconductor device comprises a plurality of semiconductor elements; and a first wire and a second wire provided to connect the semiconductor elements in parallel. The first wire and the second wire include respective wires formed in multiple wiring layers. Each wiring layer includes the first wire and the second wire formed alternately and in parallel. The wires are formed as to intersect each other in adjacent wiring layers. The first wires are connected with each other through a via-connection at an intersection of the first wires and the second wires are connected with each other through a via-connection at an intersection of the second wires.
Claims19
A semiconductor device, comprising;
- a plurality of semiconductor elements;
- and
- a first wire and a second wire provided to connect said semiconductor elements in parallel,
- wherein said first wire and said second wire include respective wires in multiple wiring layers,
- wherein each wiring layer includes said first wire and said second wire arranged alternately and in parallel,
- wherein said wires intersect each other in adjacent wiring layers, and said first wires are connected with each other through a via-connection at an intersection of said first wires and said second wires are connected with each other through a via-connection at an intersection of said second wires,
- and wherein when Ltotal denotes a total length in a wire stretching direction of an effective portion of the elements, the total length Ltotal of the elements is set to have a value of:
- Ltotal<jEM(max)·t·i(μm)/2, where t denotes a thickness of the wires in a highest wiring layer, i (μm) denotes a current flowing in the elements per unit length (1 μm) and jEM (max) denotes an Electro-Migration tolerance of a material of the wires in the highest wiring layer.
5 more elements
A semiconductor device, comprising:
- a plurality of semiconductor elements;
- and
- a first wire and a second wire provided to connect said semiconductor elements in parallel,
- wherein said first wire and said second wire include respective wires in multiple wiring layers,
- wherein each wiring layer includes said first wire and said second wire arranged alternately and in parallel,
- wherein said wires intersect each other in adjacent wiring layers, and said first wires are connected with each other through a via-connection at an intersection of said first wires and said second wires are connected with each other through a via-connection at an intersection of said second wires,
- wherein said wiring layers include at least three layers, with the wires in a second and higher layers being wider than the wires in a first layer directly connected to said semiconductor elements,
- and wherein when Ltotal denotes a total length in a wire stretching direction of an effective portion of the elements, the total length Ltotal of the elements is set to have a value of:
- Ltotal<jEM(maX)·t·i(μm)/2, where t denotes a thickness of the wires in a highest wiring layer, i(μm) denotes a current flowing in the elements per unit length (1 μm) and jEM (max) denotes an Electro-Migration tolerance of a material of the wires in a highest layer.
6 more elements
A semiconductor device, comprising:
- a semiconductor element group including a plurality of semiconductor elements each having first and second impurity-diffused layers serving as first and second main current terminals formed in a semiconductor substrate and a control electrode formed across said diffused layers via an insulator, said plurality of semiconductor elements being formed such that a first diffused region extending in a straight line connecting said first impurity-diffused layers and a second diffused region extending in a straight line connecting said second impurity-diffused layers are arranged in parallel and alternately;
- a first wire connected to said first diffused region in said semiconductor element group;
- and
- a second wire connected to said second diffused region in said semiconductor element group,
- wherein said first wire and said second wire include respective wires in multiple wiring layers,
- wherein each wiring layer includes said first wire and said second wire arranged alternately and in parallel,
- wherein in a first wiring layer directly connected to said first and second diffused regions, said first wire and said second wire extend along said first diffused region and said second diffused region, respectively,
- wherein said wires intersect each other in adjacent wiring layers, and said first wires are connected with each other through a via-connection at an intersection of said first wires and said second wires are connected with each other through a via-connection at an intersection of said second wires,
- wherein said plurality of wiring layers include wires in a second and higher layers wider than the wire in said first layer,
- and wherein when Ltotal denotes a total length in a wire stretching direction of an effective portion of the elements, the total length Ltotal of the element is set to have a value of:
- Ltotal<jEM(max)·t·i(μm)/2, where t denotes a thickness of the wires in a highest wiring layer, i(μm) denotes a current flowing in the elements per unit length (1 μm) and jEM(max) denotes an Electro-Migration tolerance of a material of the wires in the highest wiring layer.
8 more elements
Dependencies are inferred from the claim text.