US 7,622,755 B2 · Primitive cell that is robust against ESD

Abstract

A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a control voltage is applied and which has a plurality of fingers. The low finger NMOS transistor has a first terminal connected to a low power source, a gate to which the control voltage is applied and which has a plurality of fingers, and a second terminal connected to a second terminal of the PMOS transistor. The number of the fingers of the gate of the NMOS transistor is smaller than the number of fingers of the gate of the PMOS transistor and the length of each of the fingers of the NMOS transistor is greater than the length of each of the fingers of the PMOS transistor.

Claims12

Dependent claims

A primitive cell, comprising:

a high finger PMOS transistor comprising:
a first terminal connected to a high power source;
and a gate to which a control voltage is applied and which has a plurality of fingers;
and
a low finger NMOS transistor comprising:
a first terminal connected to a low power source;
a gate to which the control voltage is applied and which has a plurality of fingers;
and a second terminal connected to a second terminal of the high finger PMOS transistor,
wherein the number of fingers of the gate of the low finger NMOS transistor is smaller than the number of fingers of the gate of the high finger PMOS transistor and the fingers of the high finger PMOS transistor extend along a narrow width of an active region and the fingers of the low finger NMOS transistor extend along a wide width of another active region.

6 more elements

Dependencies are inferred from the claim text.

Primitive cell that is robust against ESD

Life of this patent

Primitive cell that is robust against ESD

Life of this patent

Abstract

Claims12