Selective contact formation using masking and resist patterning techniques

A method for manufacturing a semiconductor device including selective conductive contacts, the method comprising:

• depositing a first layer of resist over first and second memory device components, each of the first components comprising a control gate formed on a substrate, and each of the second components comprising junctions formed in the substrate and a control gate formed on the substrate between the junctions;
• polishing the first layer of resist and thereby exposing at least the first component control gates but not the substrate surrounding the first component control gates;
• depositing a second layer of resist onto the first layer of resist and over the first components, leaving an exposed region of the first resist surrounding the second components;
• simultaneously removing the entire second layer of resist, and the exposed region of the first layer of resist, and thereby exposing each of the second component control gates and junctions;
• and
• forming conductive contacts on the exposed first component control gates, and the second component control gates and junctions.