Method for fabricating a transistor using a SOI wafer
AssigneeDongbu HiTek Co., Ltd.
InventorJeong Ho Park
Life of this patent
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Abstract
Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device isolation insulation layer exposing the top surface of the first gate conductive layer pattern may be formed. A second gate conductive layer may be formed. A mask pattern may be formed. Then, a gate may be formed by etching. After forming a source and drain conductive layer on the silicon layer pattern, the mask pattern may be removed. A salicide layer may be selectively contacting the gate and the source and drain conductive layer may be formed.
Claims13
A method comprising:
- forming a first gate conductive layer pattern, a gate insulation layer pattern, and a silicon layer pattern over an SOI substrate comprising a substrate layer, a middle insulation layer formed over the substrate layer and a silicon layer formed over the middle insulation layer, wherein the silicon layer pattern is formed by etching the silicon layer;
- forming device isolation insulation layers over and contacting the middle insulation layer;
- forming a gate by forming a second gate conductive layer over the first gate conductive layer pattern and then etching the first gate conductive layer pattern and the second gate conductive layer to also form first gate conductive layer spacers on and contacting the gate insulating layer pattern and a sidewall of the device isolation insulation layers;
- forming insulating layer spacers spaced apart from a respective first gate conductive layer spacer and on and contacting sidewalls of the gate;
- forming a source and drain conductive layer adjacent to and contacting the first gate conductive layer spacers and the insulating layer spacers and over and contacting an exposed portion of the SOI substrate;
- forming a salicide layer over each of the gate and the source and drain conductive layer.
A method comprising:
- providing a SOI substrate comprising a substrate layer, an insulation layer formed over and contacting the substrate layer, and a silicon layer formed over and contacting the insulation layer;
- forming a silicon layer pattern by etching the silicon layer, a first gate insulating layer pattern over and contacting the silicon layer pattern, a first gate conductive layer pattern over and contacting the first gate insulating layer pattern, and a second gate conductive layer pattern over and contacting the first gate conductive layer pattern, a device isolation insulation layer spaced apart from the first and second gate conductive layer patterns and over and contacting the insulation layer of the SOI substrate and a sidewall of the silicon layer pattern, and a first gate conductive layer pattern spacer over and contacting a sidewall of the device isolation insulation layer;
- forming an insulating layer spacer over and contacting the uppermost surface of the first gate insulating layer pattern and a sidewall of the first and second gate conductive layer patterns;
- forming a source and drain conductive layer between the device isolation insulation layer and the first and second gate conductive layer patterns and over and contacting the uppermost surface of the silicon layer pattern and a respective sidewall of the insulating layer spacer, the first gate insulating layer pattern and the first gate conductive layer pattern spacer.
Dependencies are inferred from the claim text.