Method for forming contacts of semiconductor device

#The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2006-0085482 (filed on Sep. 6, 2006) which is hereby incorporated by reference in its entirety.

#Electronic devices such as computers and televisions incorporate within there operating structure semiconductor devices such as diodes or transistors. Such semiconductor devices may be manufactured through a series of processes of forming a film on a wafer. The semiconductor wafer may be created by growing silicon oxide and implanting impurity ions into required portions of the silicon dioxide film to electrically activate the portions and then connecting wirings between the portions.

#As a result of an increase in the integration density of semiconductor devices, it may prove difficult to drive semiconductor devices using one metal wiring layer. Accordingly, the development and use of multilayer semiconductor devices has become prevalent. An interlayer insulating layer is formed between conducting layers of a multilayer semiconductor device in order to provide insulation between the conducting layers. In order to electrically connect the stacked conducting layers, it may be necessary to perform a separate contact process in which contact holes are formed in the interlayer insulating layer and the contact holes subsequently filled with a electrically conducting material. A reduction in size of the semiconductor device and the line width has may become essential in addition to an increase in the integration density of semiconductor devices. Accordingly, technologies for implementing fine line widths have become important in the fabrication of semiconductor devices. There are many limitations and difficulties when patterning narrower lines and smaller contact holes.

#Example FIG. 1 illustrates a method for forming contacts of a semiconductor device.

#Example FIGS. 2A to 2C illustrate a method for forming contacts of a semiconductor device, in accordance with embodiments.

#As illustrated in example FIG. 2A, wiring layer 201 is formed on and/or over a semiconductor substrate. Diffusion barrier layer 202 is formed on metal wiring layer 201. Diffusion barrier layer may be composed of a material such as titanium (Ti) and/or titanium nitride (TiN). Wiring layer 201 may be composed of a metal such as aluminum (Al). Interlayer insulating layer 203 is formed on and/or over metal wiring layer 201 and diffusion barrier layer 202. A low-k material such as un-doped silicate glass (USG) and fluorinated silicate glass (FSG) may be used to form interlayer insulating layer 203 and deposited using a high density plasma chemical vapor deposition (HDP-CVD). Thereafter, capping layer 204 is formed on and/or over interlayer insulating layer 203 to prevent diffusion of fluorine (F) into interlayer insulating layer 203. Capping layer 204 may be composed of SiH4-rich oxide, which contains a large amount of silicon hydride (SiH4).

#Hard mask layer 205 is formed on and/or over capping layer 204 to prevent the occurrence of tapering during plasma treatment prior to formation of a photoresist layer on and/or over capping layer 204. Hard mask layer 205 may be formed using a SiN material through a plasma enhanced chemical vapor deposition (PE-CVD). Hard mask layer 205 is preferably formed to a thickness of approximately between 350 Å to 400 Å.

#The formation of vias are done by coating a photoresist material on hard mask layer 205 and then selectively exposing the photoresist material to light, developing and then patterning the photoresist material. Accordingly, a plurality of photoresist patterns 206 may be formed at specific intervals on hard mask layer 205. Here, photoresist patterns 206 may be formed to a thickness of between approximately 6000 Å to 8000 Å.