System for checking clock-signal correspondence

A method for detecting a time difference between clock edges in an integrated circuit, said method comprising the steps of:

• receiving a first clock signal at a first input port;
• receiving a second clock signal at a second input port;
• checking for a correspondence between a clock edge of said first clock signal and a corresponding clock edge of said second clock signal within a predetermined time window;
• wherein said checking is performed during operation of said integrated circuit;
• wherein said checking is performed by checking logic comprising a reference signal path and a further signal path;
• and wherein said further signal path comprises at least one data capture element clocked by said first clock signal and at least one data capture element clocked by said second clock signal.

Apparatus for processing data comprising:

• a first set of processing logic circuitry corresponding to a first clock domain clocked by a first clock signal;
• a second set of processing logic circuitry corresponding to a second clock domain clocked by a second clock signal;
• a frequency controller configured to vary a frequency of at least one of said first clock signal and said second clock signal;
• a clock-signal comparator having:
• a first input port for receiving said first clock signal;
• a second input port for receiving said second clock signal;
• and
• checking logic circuitry configured to check for a correspondence between a clock edge of said first clock signal and a corresponding clock edge of said second clock signal within a predetermined time window;
• wherein said checking logic circuitry is configured to check for said correspondence during operation of said data processing apparatus;
• wherein said apparatus further comprises a synchroniser configured in an asynchronous mode of said data processing apparatus to synchronise communication between said first clock domain and said second clock domain.

A computer-readable medium comprising a hardware description model of a circuit in a hardware description language, said hardware description model comprising representations of:

• a clock-signal comparator having:
• a reference input port for receiving a reference clock signal;
• at least one further input port for receiving a respective further clock signal;
• and
• checking logic circuitry configured to check for a correspondence between a clock edge of said reference clock signal and a corresponding clock edge of said further clock signal within a predetermined time window;
• wherein said checking logic circuitry is configured to check for said correspondence during operation of said circuit, wherein said checking logic circuitry comprises a reference signal path and a further signal path, and wherein said further signal path comprises at least one data-capture element clocked by said reference clock and at least one data-capture element clocked by said further clock.

A computer program stored on a computer-readable medium, the computer program being for simulating the operation of a data processing apparatus having at least one processing unit, said computer program comprising:

• hardware description language code comprising a plurality of hardware description language code modules representing respective ones of said at least one processing unit;
• event simulator code configured to execute said hardware description language code to simulate operation of said data processing apparatus and to generate a plurality of signal values and corresponding signal times for a respective plurality of simulated signals;
• one of said plurality of hardware description language code modules representing a processing unit comprising:
• a clock-signal comparator having:
• a reference input port for receiving a reference clock signal corresponding to one of said plurality of simulated signals;
• at least one further input port for receiving a respective further clock signal corresponding to a different one of said plurality of simulated signals;
• and
• checking logic configured to check for a correspondence between a clock edge of said reference clock signal and a corresponding clock edge of said further clock signal within a predetermined time window;
• wherein said checking logic circuitry is operable to check for said correspondence when said event simulator code is executing said hardware description language code, wherein said checking logic circuitry comprises a reference signal path and a further signal path, and wherein said further signal path comprises at least one data-capture element clocked by said reference clock and at least one data-capture element clocked by said further clock.

A method for checking for timing errors in a simulation of the operation of a data processing apparatus having at least one processing unit, said method comprising the steps of:

• providing hardware description language code comprising at least one hardware description language code modules representing said at least one processing unit;
• executing said hardware description language code on an event simulator to simulate operation of said data processing apparatus and generating a plurality of signal values and corresponding signal times for a respective plurality of simulated signals;
• wherein one of said at least one hardware description language code module represents a processing unit comprising:
• a clock-signal comparator having:
• a reference input port for receiving a reference clock signal corresponding to one of said plurality of simulated signals;
• at least one further input port for receiving a respective further clock signal corresponding to a different one of said plurality of simulated signals;
• and
• checking logic circuitry configured to check for a correspondence between a clock edge of said reference clock signal and a corresponding clock edge of said further clock signal within a predetermined time window;
• and
• wherein said checking logic circuitry is configured to identify said timing errors by checking for said correspondence when said event simulator code is executing said hardware description language code, wherein said checking logic circuitry comprises a reference signal path and a further signal path, and wherein said further signal path comprises at least one data-capture element clocked by said reference clock and at least one data-capture element clocked by said further clock.