Method to implement metal fill during integrated circuit design and layout

A system operable to implement metal fill within an integrated circuit (IC), the system comprising:

• a layout tool operable to facilitate an integrated circuit (IC) design, wherein the layout tool:
• defines each conductive layer as a plurality of conductive traces regularly spaced according to a set of design rules;
• and
• forms active segments and inactive segments within the conductive traces with design rule compliant cuts, wherein:
• active segments of the conductive traces are initially operable to electrically couple to circuit devices within other layers to form electrical circuits within a IC;
• and
• inactive segments of the conductive traces are initially operable to be electrically isolated from circuit devices within other layers and to reduce process variation during fabrication of the IC;
• and
• a verification tool operable to verify the IC design, wherein the verification tool extracts physical characteristics associated with the IC to verify the IC design, wherein the physical characteristics include electrical characteristics of the active segments and electrical characteristics of the inactive segments;
• wherein:
• the verification tool is operable to identify problematic electrical circuits having blockages within active segments thereof;
• and
• the layout tool is operable to reroute problematic electrical circuits with inactive segments of the conductive traces.

A method operable to implement metal fill within an integrated circuit (IC), the method comprising:

• using a computer for:
• configuring a plurality of conductive traces within a conductive layer, wherein the traces are spaced according to a set of design rules;
• making cuts compliant to the set of design rules in the conductive traces, wherein the cuts are operable to divide the conductive traces into active segments and inactive segments;
• coupling active segments of the conductive traces initially with circuit devices within other layers to form electrical circuits;
• and
• electrically isolating the inactive segments of the conductive traces initially from circuit devices within other layers to reduce process variation during fabrication of the IC;
• identifying problematic electrical circuits having blockages within active segments thereof;
• identifying inactive segments operable to reroute the problematic electrical circuits;
• and
• rerouting the problematic electrical circuits by coupling electrically the identified inactive segments with circuit devices within other layers to form rerouted electrical circuits.

A metal fill layer, comprising:

• a plurality of conductive traces regularly spaced according to a set of design rules;
• and
• a plurality of design rule compliant cuts in the conductive traces operable to electrically separate segments of the conductive traces into active segments and inactive segments, wherein:
• active segments of the conductive traces are operable to initially electrically couple to circuit devices within other layers to form electrical circuits within an integrated circuit (IC);
• inactive segments of the conductive traces are initially operable to be electrically isolated from circuit devices within other layers and to reduce process variation during fabrication of the IC;
• and
• electrical circuits having blockages within active segments are operable to be rerouted to inactive segments using vias in dielectric layers adjacent to conductive layers to electrically couple the previously inactive segments with circuit devices within other layers.