Testing for bridge faults in the interconnect of programmable integrated circuits

A method of testing for bridge faults in nets of a programmable integrated circuit, the method comprising:

• grouping a plurality of nets;
• configuring function generators as shift registers such that each of the plurality of nets is sourced by a function generator, wherein the configuring comprises for each net group:
• initializing identically to one value shift registers coupled to nets in the net group;
• initializing shift registers coupled to nets in the net group to a different unique value from shift registers coupled to nets of other net groups;
• and
• storing in each shift register of the net group one bit with a value of one and with zeros in all other bits in nets of the programmable integrated circuit so that when clocked, each shift register provides a single one on one clock cycle and provides zeros on all other clock cycles;
• clocking the shift registers;
• and
• providing an indication with a test device coupled to the net groups when a short is detected between net groups by testing the net groups after each clock cycle.