US 7,614,020 B2Granted

Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems

AssigneeiKoa Corporation

InventorsShridhar Mukund, Anjan Mitra

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Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

Claims17

Dependent claims

A structurally reconfigurable semiconductor circuit device for in-memory processing of stateful, transaction-oriented applications, comprising:

a multiple level array of memory storage cells and logic circuits, the storage cells having multiple configurable access paths, the storage cells capable of being simultaneously accessed for being read from and written into;
a plurality of configurable, packetized interface ports capable of receiving data packets, the packetized interface ports having access to the multiple level array;
a plurality of configurable commute elements distributed within the multiple level array, each of the plurality of configurable commute element configured to move data within the multiple level array of storage cells through one of the multiple configurable access paths;
a plurality of configurable Compute elements within the multiple level array, each of the plurality of configurable Compute elements configured to transform data within a portion of the multiple level array of storage cells via the multiple configurable access paths;
and
a pool of redundant features for repairing a defective feature within the multiple level array, wherein levels of the multiple level array associated with a higher defect density have more redundant features available for repair relative to levels associated with a lower defect density.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/426,880Filed 27 Jun 2006 · us provisional application
Priority: 27 Jun 2005
Published: US 2006/0294483 A128 Dec 2006
Granted: 3 Nov 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 15/7821
System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package: tightly…
G06F 15/7867
Comprising a single central processing unit: with reconfigurable architecture
G06F 30/30
Computer-aided design [CAD]: circuit design
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Family

Application60/694,538Us provisional application · filed 27 Jun 2005
Application60/694,546Us provisional application · filed 27 Jun 2005
Application60/694,537Us provisional application · filed 27 Jun 2005
US 2006/0294483 A1Pre-grant publication · published 28 Dec 2006
US 7,614,020 B2This patent

From the US filing history. Foreign family members aren’t listed.

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