Method and apparatus for concurrent calculation of cyclic redundancy checks
AssigneeAltera Corporation
InventorPeter Bain
Life of this patent
Estimating the term…
Abstract
Circuits and methods provide the concurrent calculation of CRC bits for messages from different channels, where one part of a message is received at a time. Context buffers store certain state variables of the CRC calculation for each channel. The context buffers output data in a synchronized manner with the input data so that the proper calculations are done and the proper data is available at the appropriate times.
Claims22
An integrated circuit including a CRC circuit that receives a plurality of messages, each from one of a plurality of channels, and provides CRC bits for each message, wherein a message is composed of a plurality of words, the CRC circuit comprising:
- a feedforward circuit that serially receives the words of the messages and provides a feedforward result from a received word to a first summing circuit;
- a feedback circuit that is coupled with an output of the first summing circuit and that provides a feedback result to an input of the first summing circuit, wherein the feedback circuit includes a first timing device;
- and
- a first context buffer having an input coupled with an output of the first timing device and having an output coupled with an input of the first summing circuit, wherein the first context buffer is on a signal path between the first timing device and the summing circuit,
- wherein the first context buffer stores the feedback results for at least two messages of different channels and outputs a feedback result for a specific channel to be summed with a feedforward result for that specific channel.
An integrated circuit including a CRC circuit that receives a plurality of messages, each from one of a plurality of channels, and provides CRC bits for each message, wherein a message is composed of a plurality of words, the CRC circuit comprising:
- a feedforward circuit that serially receives the words of the messages and provides a feedforward result from a received word to a first summing circuit;
- a feedback circuit that is coupled with an output of the first summing circuit and that provides a feedback result to an input of the first summing circuit, wherein the feedback circuit includes a first timing device;
- and
- a first context buffer having an input coupled with the first timing device and having an output coupled with the first summing circuit,
- wherein the first context buffer stores the feedback results for at least two messages of different channels and outputs a feedback result for a specific channel to be summed with a feedforward result for that specific channel, wherein the CRC circuit further comprises:
- a second timing device that receives a first CRC result from the first summing circuit;
- and
- a second context buffer having an input coupled with the second timing device and having an output coupled with the first timing device, wherein the second context buffer stores the first CRC results for at least two messages of different channels.
An integrated circuit including a CRC circuit that receives a plurality of messages, each from one of a plurality of channels, and provides CRC bits for each message, wherein a message is composed of a plurality of words, the CRC circuit comprising:
- a feedforward circuit that serially receives the words of the messages and provides a feedforward result from a received word to a first summing circuit;
- a feedback circuit that is coupled with an output of the first summing circuit and that provides a feedback result to an input of the first summing circuit, wherein the feedback circuit includes a first timing device;
- and
- a first context buffer having an input coupled with the first timing device and having an output coupled with the first summing circuit,
- wherein the first context buffer stores the feedback results for at least two messages of different channels and outputs a feedback result for a specific channel to be summed with a feedforward result for that specific channel, wherein the first context buffer outputs a feedback result during a same clock cycle that the feedback result is received, when a current context channel signal has a same value as an immediately previous context channel signal.
A method of computing CRCs for a plurality of messages from a plurality of channels, wherein a message is composed of a plurality of words, each associated with the channel of that message, the method comprising:
- serially receiving a plurality of words at a feedforward circuit such that the words of different messages are interspersed with each other;
- for each received word:
- calculating a feedforward result;
- and
- transmitting the feedforward result to a first summing circuit;
- and
- transmitting a CRC result from the first summing circuit to a feedback loop having an output coupled with an input of the first summing circuit and having one or more stages, wherein each stage has a corresponding feedback state variable;
- during a clock cycle associated with a current channel:
- providing each of the feedback state variables of a previous channel to a respective context buffer;
- and
- outputting each of the state variables of the current channel from one of the respective context buffers;
- and
- summing a final feedback state variable of the current channel with a feedforward result of the current channel to form a first CRC.
An integrated circuit including a CRC circuit that receives a plurality of messages, each from one of a plurality of channels, wherein a message is composed of a plurality of words, the CRC circuit comprising:
- a feedforward circuit that serially receives words and for each word provides a feedforward state variable to a first summing circuit;
- a feedback loop that is coupled with an output of the first summing circuit and that provides a feedback state variable to an input of the first summing circuit, wherein the feedback loop includes N timing devices and N logic blocks, each logic block producing an Nth state variable;
- and
- N feedback context buffers, wherein one feedback context buffer is between each of the N timing devices and one feedback context buffer is between the Nth timing device and the first summing circuit,
- wherein each of the N feedback context buffers stores state variables for at least two messages of different channels and outputs a state variable for a specific channel based on a channel indicator, wherein N is a positive integer greater than or equal to one.
Dependencies are inferred from the claim text.