Data processing apparatus and method for flash memory

A data processing apparatus for a flash memory comprising:

• an extraction unit which extracts from memory regions of the flash memory error correction code (ECC) and inverted data, the inverted data being obtained before a data operation requested by a user is performed by inverting generated ECC loaded in a buffer, the generated ECC generated from data loaded into the buffer to be used in the data operation not yet performed, the extracted ECC and the extracted inverted data each corresponding to data located at a logical address;
• and
• a control unit which determines whether the extracted ECC is erroneous and a number of erroneous bits included in the extracted ECC with reference to a relationship between the extracted ECC and the extracted inverted data,
• wherein the extracted inverted data and the extracted ECC are mutually exclusive of each other.

A data processing method for a flash memory comprising:

• issuing a request for performing a data operation on a flash memory using a logical address;
• converting the logical address into a physical address;
• before performing the data operation, obtaining inverted data by inverting a generated error correction code (ECC) loaded in a buffer corresponding to data loaded in the buffer which is to be used in the data operation, and loading the inverted data into the buffer;
• performing the data operation on the physical address, writing inverted data loaded in the buffer and obtained by inverting the generated error correction code (ECC) corresponding to data used in the data operation to an inverted data region of the flash memory, and writing the generated ECC from the buffer to an ECC region of the flash memory to be extracted from the ECC region as an extracted ECC, the inverted data used to indicate whether an-the extracted ECC stored in the ECC region of the flash memory is erroneous,
• wherein the inverted data and the extracted ECC are mutually exclusive of each other.

A data processing method for a flash memory comprising:

• extracting error correction code (ECC) and inverted data, the inverted data being obtained by inverting generated ECC loaded in a buffer and generated from data loaded into the buffer to be used in the data operation not yet performed, the extracted ECC and the extracted inverted data each corresponding to data located at a logical address;
• and
• determining whether the extracted ECC is erroneous and a number of erroneous bits included in the extracted ECC with reference to a relationship between the extracted ECC and the extracted inverted data,
• wherein the extracted inverted data and the extracted ECC are mutually exclusive of each other.

A data processing apparatus of a flash memory comprising:

• a user request unit which issues a request for performing a data operation on a flash memory using a logical address;
• a conversion unit which converts the logical address into a physical address;
• a control unit which, before performing the data operation, generates error correction code (ECC) corresponding to data loaded in a buffer to be used in the data operation not vet performed and loads the generated ECC into the buffer, generates inverted data by inverting the generated ECC loaded into the buffer, performs the data operation on the physical address using the data, and writes the inverted data and the generated ECC to the flash memory while performing the data operation;
• and
• an extraction unit which extracts the ECC and the inverted data written to the flash memory;
• wherein the control unit determines whether the extracted FCC is erroneous and a number of erroneous bits included in the extracted ECC with reference to a relationship between the extracted ECC and the extracted inverted data, and
• the extracted inverted data and the extracted ECC are mutually exclusive of each other.