System and method for reducing power consumption in a low-density parity-check (LDPC) decoder

A method for reducing power consumption in a Low Density Parity Check (LDPC) decoder, wherein the LDPC decoder comprises a plurality of Bit Node Memory Units (BNMUs) corresponding to a plurality of bit nodes, a plurality of Check Node Memory Units (CNMUs) corresponding to a plurality of check nodes, and a plurality of Check Node and Bit Node Update Units (CNBNUs), each BNMU having at least one bit node from the plurality of bit nodes, wherein each of the at least one bit nodes is used for storing a bit node message value corresponding to one of the check nodes, each CNMU having at least one check node from the plurality of check nodes, wherein each of the at least one check nodes is used for storing check node message values corresponding to one or more of the bit nodes, each CNBNU associated with a check node and being used for updating the check node and one or more bit nodes corresponding to the check node in one or more iterations of an exchange of messages between the check node and the one or more bit nodes, the method comprising the steps of:

• selecting a check node for updating, wherein updating the check node comprises modifying the check node message value corresponding to the check node and the bit node message value corresponding to each of the one or more bit nodes corresponding to the check node;
• checking whether the check node is in a sleep mode, wherein the check node is in the sleep mode when an absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value;
• and
• turning OFF a CNBNU associated with the check node when the check node is in the sleep mode, wherein turning OFF the CNBNU stops the exchange of messages between the check node and the corresponding one or more bit nodes.

A Low Density Parity Check (LDPC) decoder, comprising:

• a plurality of Bit Node Memory Units (BNMUs) corresponding to a plurality of bit nodes, each BNMU having at least one bit node from the plurality of bit nodes;
• a plurality of Check Node Memory Units (CNMUs) corresponding to a plurality of check nodes, each CNMU having at least one check node from the plurality of check nodes, wherein each of the at least one check nodes stores a check node message value corresponding to one or more of the bit nodes, and wherein each of the at least one bit nodes stores a bit node message value corresponding to a check node;
• a plurality of Check Node and Bit Node Update Units (CNBNUs), wherein each CNBNU updates a check node and one or more of the bit nodes corresponding to said check node in one or more iterations of an exchange of messages between check node and the one or more bit nodes;
• a sleep mode checking module that checks whether a check node is in a sleep mode, wherein the check node is in the sleep mode when an absolute value of a message going to each of one or more bit nodes corresponding to the check node is greater than a threshold value;
• and
• a gating circuit that gates turns OFF a CNBNU associated with the check node when the check node is in the sleep mode, wherein turning OFF the CNBNU stops the exchange of messages between the check node and the one or more bit nodes.