Method for providing bitwise constraints for test generation

A method incorporated in a computer system for providing a bitwise constraint for computer based test generation for design verification via device simulation, the method comprising:

• providing in the computer system a language structure for expressing the bitwise constraint, said language structure including one or more constraint parameters and at least one operator, said constraint parameter having a range list containing at least one value;
• operating the computer system to propagate information bi-directionally to determine limits for said constraint parameters;
• and
• generating a test value for the bitwise constraint.

A method for providing a bitwise constraint and a range list constraint, for computer-based test generation for design verification via device simulation, with an arithmetic range list, the arithmetic range list containing at least one arithmetic value, the method comprising:

• providing a means for establishing a language structure, said language structure expressing the bitwise constraint with regard to the arithmetic range list in parallel to the range list constraint, said language structure including one or more constraint parameters for the bitwise constraint and for the range list constraint and at least one operator;
• providing a means for propagating information bi-directionally to determine limits for said constraint parameters;
• and
• providing a means for generating a test value for the bitwise constraint, thereby to resolve both an arithmetic constraint and said bitwise constraint together.

A method for bitwise representation of a range list having an arithmetic constraint and a bitwise constraint for compute-based test generation for design verification via device simulation, the method comprising:

• providing a test engine including a test generator;
• executing said teat generator to translate the range list to a bitwise list;
• and
• executing said test generator to generate a test, the test generator solving the arithmetic constraint together with the bitwise constraint while using one or both of the range list and said bitwise list thereby to resolve both the arithmetic constraint and said bitwise constraint together.

A method of computer-based test generation for design verification via device simulation for a range list having an arithmetic constraint and a bitwise constraint, comprising:

• providing a system having distinct modules, and wherein the distinct modules include a range list translation module, and a bitwise constraint application module;
• providing a computational structure for containing the range list and a bitwise representation of the range list;
• translating the range list to provide said bitwise representation of the range list, wherein the translating the range list is performed by the range list translation module;
• and
• applying the bitwise constraint to said bitwise representation and the arithmetic constraint to the range list to perform the test generation, thereby to resolve both said arithmetic constraint and said bitwise constraint together, wherein the applying the bitwise constraint is performed by the bitwise constraint application module.

A computer program product for use with a computer, the computer program product comprising a computer usable storage medium having a computer readable program code embodied therein adapted to be executed to implement a method in computer based test generation, for design verification via device simulation, for bitwise representation of a range list having an arithmetic constraint and a bitwise constraint, comprising:

• translating the range list to provide the bitwise representation of the range list;
• propagating the arithmetic constraint and the bitwise constraint to determine at least one new range according to both the arithmetic constraint and the bitwise constraint;
• and
• computing one or more permissible values for a constraint parameter, thereby to resolve said arithmetic and bitwise constraints together.