Semiconductor integrated circuit, and designing method and testing method thereof

A semiconductor integrated circuit designing method comprising the steps of:

• designing a semiconductor integrated circuit having
• a combinational circuit section having a combinational circuit,
• a clock control section for generating and outputting a predetermined number of pulses as a first clock signal after a predetermined period has passed since a time when a change in a scan enable signal was received,
• a clock stop control circuit for controlling an enable state and a disable state of the first clock signal based on the scan enable signal, and for outputting a controlled clock signal as a second clock signal, and
• a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with the first and the second clock signals,
• where the clock control section has an oscillator circuit for generating and outputting the pulses, and is configured to output a last pulse of the predetermined number of pulses in a manner which holds a logical value immediately after an active edge of the last pulse;
• and
• inserting a delay circuit for delaying the scan enable signal so that a change in the scan enable signal reaches the clock control section later than the change in the scan enable signal reaches the clock stop control circuit.