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US 7,613,971 B2Granted
Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit
AssigneeNEC Electronics Corporation
InventorToshiharu Asaka
Life of this patent
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Abstract
A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.
Claims12
A semiconductor integrated circuit comprising:
- a first input side flip-flop;
- a first combinational circuit having an input connected with said first input side flip-flop;
- an output side flip-flop connected with an output of said first combinational circuit;
- a second input side flip-flop;
- a second combinational circuit having an input connected with said second input side flip-flop and an output connected with said first input side flip-flop;
- and
- a delay test circuit,
- wherein said delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies said output clock pulses to said first input side flip-flop, said output side flip-flop and said second input side flip-flop;
- wherein:
- said first combinational circuit is a multi-cycle path and receives a first input data from said first input side flip-flop to output a first output data indicating an operation result of said first input data to said output side flip-flop;
- said second combinational circuit is a single-cycle path and receives a second input data from said second input side flip-flop to output a second output data indicating an operation result of said second input data to said first input side flip-flop;
- said first input side flip-flop and said second input side flip-flop output said first input data and said second input data to said first and second combinational circuits, respectively, in response to an edge of a first one of said output clock pulses;
- said output side flip-flop and said first input side flip-flop simultaneously receive said first output data and said second output data therefrom, respectively, in response to an edge of a second one of said output clock pulses;
- and
- a time interval between said edge of said first one of output clock pulses and said edge of said second one of output clock pulses corresponds to a first combinational circuit data transfer.
12 more elements
A semiconductor integrated circuit comprising;
- a first flip-flop outputting a first input data in response to a first edge of a clock signal;
- a first combinational circuit coupled to said first flip-flop and receiving said first input data therefrom to output a first output data indicating an operation result of said first input data, wherein said first combination circuit is a single-cycle path;
- a second flip-flop coupled to said first combinational circuit to receive said first output data in response to a second edge of said clock signal, said second edge being subsequent to said first edge, wherein said second flip-flop outputs a second input data in response to said first edge of said clock signal;
- a second combinational circuit coupled to said second flip-flop and receiving said second input data therefrom to output a second output data indicating an operation result of said second input data, wherein said second combinational circuit is a multi-cycle path;
- a third flip-flop coupled to said second combinational circuit to receive said second output data in response to said second edge of said clock signal;
- and
- a delay test circuit coupled to said first, second and third flip-flops respectively to supply said clock signal thereto, wherein a time interval between said first edge of said clock signal and said second edge of said clock signal corresponds to a second combinational circuit data transfer,
- wherein said second and third flip-flops simultaneously receive said first and second output data respectively in response to said second edge of said clock signal.
5 more elements
Dependencies are inferred from the claim text.