Back to results
US 7,613,969 B2Granted
Method and system for clock skew independent scan register chains
AssigneeCadence Design Systems, Inc.
InventorSandeep Bhatia
Life of this patent
Estimating the term…
Abstract
A method and system for clock skew independent scan chains. In one embodiment, a method comprises connecting a plurality of mux-D scan registers in a chain configuration, wherein a first mux-D scan register of the plurality is associated with a first clock network, and a second mux-D scan register of the plurality is associated with a second clock network. The plurality of mux-D scan registers have a scan mode. The first mux-D scan register and the second mux-D scan register become clock skew independent by controlling a scan-enable signal and a clock signal.
Claims14
A method, comprising:
- operating a tester to assert a scan-enable signal;
- asserting the scan enable signal to an inactive value during a scan data capture cycle, wherein the inactive value is equivalent to a logic low;
- pulsing a clock signal during the capture cycle;
- asserting the scan enable signal to an active value during a shift scan cycle, wherein the active value is equivalent to a logic high;
- locking scan data into a first master latch of a negative-edge triggered scan register having the first master latch and a first slave latch when the clock signal has a falling edge;
- asserting the scan enable signal to the inactive value;
- transferring the scan data from the first master latch to the first slave latch to compensate for clock skew;
- asserting the scan enable signal to the active value;
- locking the scan data into a second master latch of a positive-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a rising edge;
- and
- asserting the scan enable signal to the inactive value;
- and
- transferring the scan data from the second master latch to the second slave latch to compensate for clock skew.
10 more elements
A method, comprising:
- operating a negative-edge triggered mux-D scan register in scan mode;
- operating a tester to assert a scan-enable signal;
- gating a clock signal to a first slave latch of the negative-edge triggered mux-D scan register having a first master latch and the first slave latch using the scan-enable signal;
- asserting the scan-enable signal to an active value during the scan mode, wherein the active value is equivalent to a logic high;
- locking scan data into the first master latch of the negative-edge triggered mux-D scan register when the clock signal has a falling edge;
- asserting the scan enable signal to an inactive value, wherein the inactive value is equivalent to a logic low;
- transferring the scan data from the first master latch to the first slave latch;
- asserting the scan enable signal to the active value;
- locking the scan data into a second master latch of a positive-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a rising edge;
- and
- asserting the scan-enable signal to the inactive value;
- and
- transferring the scan data from the second master latch to the second slave latch to compensate for clock skew.
10 more elements
A method, comprising:
- operating a tester to assert a scan-enable signal;
- operating a negative-edge triggered mux-D scan register in scan mode, the negative-edge triggered mux-D scan register having a first master latch and a first slave latch;
- including,
- asserting the scan-enable signal to an active value, wherein the active value is equivalent to a logic high;
- locking scan data into the first master latch of the negative-edge triggered mux-D scan register when a clock signal has a falling edge;
- asserting the scan enable signal to the active value;
- locking the scan data into a second master latch of a positive-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a rising edge;
- inverting the scan enable signal to generate an inverted scan enable signal;
- logically ANDing the inverted scan enable signal with the clock signal, to generate a slave latch clock signal;
- providing the slave latch clock signal to the first slave latch to transfer the scan data to the first slave latch;
- asserting the scan enable signal to an inactive value, wherein the inactive value is equivalent to a logic low;
- and
- transferring the scan data from the second master latch to the second slave latch.
10 more elements
A method, comprising:
- operating a multiplexer including a scan-in input, a data input, and a scan-enable input;
- connecting a first master latch to the multiplexer, the first master latch locking scan data into the first master latch of a negative-edge, triggered sc an register having the first master latch and a first slave latch when a clock signal has a falling edge;
- transferring the scan data from the first master latch to the first slave latch;
- locking the scan data into a second master latch of a positive-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a rising edge;
- and
- connecting a logic gate to the clock signal and to the first slave latch using a scan-enable signal provided to the scan-enable input.
3 more elements
A method, comprising:
- operating a tester to assert a scan-enable signal;
- asserting the scan enable signal to an inactive value during a scan data capture cycle, wherein the inactive value is equivalent to a logic low;
- pulsing a clock signal during the capture cycle;
- asserting the scan enable signal to an active value during a shift scan cycled, wherein the active value is equivalent to a logic high;
- locking scan data into a first master latch of a positive-edge triggered scan register having the first master latch and a first slave latch when the clock signal has a rising edge;
- asserting the scan enable signal to the inactive value;
- transferring the scan data from the first master latch to the first slave latch to compensate for clock skew;
- asserting the scan enable signal to the active value;
- locking the scan data into a second master latch of a negative-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a falling edge;
- and
- asserting the scan enable signal to the inactive value;
- and
- transferring the scan data from the second master latch to the second slave latch to compensate for clock skew.
10 more elements
A method, comprising:
- operating a tester to assert a scan-enable signal;
- operating a positive-edge triggered mux-D scan register in scan mode;
- gating a clock signal to a first slave latch of the positive-edge triggered mux-D scan register having a first master latch and the first slave latch using the scan-enable signal;
- asserting the scan-enable signal to an active value during the scan mode, wherein the active value is equivalent to a logic high;
- locking scan data into the first master latch of the positive-edge triggered mux-D scan register when the clock signal has a rising edge;
- asserting the scan enable signal to an inactive value, wherein the inactive value is equivalent to a logic low;
- transferring the scan data from the first master latch to the first slave latch;
- asserting the scan enable signal to the active value;
- locking the scan data into a second master latch of a negative-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a falling edge;
- and
- asserting the scan-enable signal to the inactive value;
- transferring the scan data from the second master latch to the second slave latch to compensate for clock skew.
9 more elements
A method. comprising:
- operating a tester to assert a scan-enable signal;
- operating a positive-edge triggered mux-D scan register in scan mode, the positive-edge triggered mux-D scan register having a first master latch and a first slave latch;
- including,
- asserting the scan-enable signal to an active value, wherein the active value is equivalent to a logic high;
- locking scan data into the first master latch of the positive-edge triggered mux-D scan register when a clock signal has arising edge;
- asserting the scan enable signal to the active value;
- locking the scan data into a second master latch of a negative-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a falling edge;
- inverting the scan enable signal to generate an inverted scan enable signal;
- logically ANDing the inverted scan enable signal with the clock signal, to generate a slave latch clock signal;
- providing the slave latch clock signal to the first slave latch to transfer the scan data to the first slave latch;
- asserting the scan enable signal to an inactive value, wherein the inactive value is equivalent to a logic low;
- and
- transferring the scan data from the second master latch to the second slave latch.
10 more elements
A method, comprising:
- operating a multiplexer including a scan-in input, a data input, and a scan-enable input;
- connecting a first master latch to the multiplexer, the first master latch locking scan data into the first master latch of a positive-edge triggered scan register having the first master latch and a first slave latch when a clock signal has a rising edge;
- transferring the scan data from the first master latch to the first slave latch;
- locking the scan data into the second master latch of a negative-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a falling edge;
- and
- connecting a logic gate to the clock signal and to the first slave latch using a scan-enable signal provided to the scan-enable input.
3 more elements
Dependencies are inferred from the claim text.