Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application

A method of designing a semiconductor integrated circuit with full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM) at internally doubled clock testing application comprising the steps of:

• including a pulse generator having an output attached to a clear input of a toggle flip-flop, and having an input which is a write line from a memory controller,
• wherein said toggle flip-flop having a data input coupled to an inverse output through a feedback of said flip-flop, said toggle flip-flop further having a clock input, and a true output,
• including an exclusive -OR circuit having one input which comes from said true output of said toggle flip-flop, having another input which is a select signal and having an output which is an external select signal, and
• including a multiplexer circuit having one input which is the positive data input-bit, having another input which is the negative data-input bit, which is the inverse of said positive data input bit, having a select line which is said external select line from said exclusive-OR circuit, having one output which is a data input-even bit and having another output which is a data input-odd bits
• wherein said integrated circuit provides full-speed testing of said synchronous dynamic random access memory (SDRAM).