Data receiving apparatus of a PCI express device
AssigneeVIA Technologies, Inc.
InventorWayne Tseng
Life of this patent
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Abstract
A data receiving apparatus of a PCI Express system includes a receiving device, an 8B10B decoder, a forged packet removing device, and a descrambling circuit. The forged packet removing device determines whether a disparity error occurs; and an offset removing circuit compensates a number of cycles of the lane offset. The data receiving apparatus is capable of eliminating error packet caused by framing error and preventing the problem of symbol disorder and disconnection caused by set ordered noise. Furthermore, the data receiving apparatus is also capable of removing offset.
Claims18
A data receiving apparatus, comprising:
- a receiving device for receiving a data signal;
- an 8B10B decoder coupled to the receiving device for decoding the data signal;
- a forged packet removing device coupled to the 8B10B decoder for outputting either the data signal from the 8B10B decoder or a symbol according to whether a disparity error occurs;
- and
- a descrambling circuit coupled to the forged packet removing device for descrambling the data signal;
- wherein if the disparity error occurs, the forged packet removing device outputs the symbol;
- if the disparity error does not occur, the forged packet removing device outputs the data signal from the 8B10B decoder.
A forged packet removing device of a data receiving apparatus for outputting either a data signal or a symbol according to whether a disparity error occurs, the forged packet removing device comprising:
- a first input end for receiving the data signal;
- a second input end for receiving a command signal for indicating whether the disparity error occurs;
- a third input end for receiving the symbol;
- and
- an output end, wherein the output end outputs the data signal while the command signal indicates the disparity error does not occur;
- and the output end outputs the symbol while the command signal indicates the disparity error occurs.
A data descrambling circuit for descrambling a data signal, comprising:
- an OR gate;
- a flip-flop;
- and
- a linear feedback shift resister (LFSR);
- wherein an input end of the LFSR is coupled to an output end of the flip-flop;
- an output end of the LFSR is coupled to an input end of the flip-flop;
- the OR gate comprises two input ends for receiving a first command and a second command respectively;
- the flip-flop is used for receiving output of the LFSR, output of the OR gate, and a predetermined value;
- the data signal comprises an ordered set for adjusting an operating clock to balance a latency of the data signal caused by the operating clock, and the ordered set comprises a COM symbol and three SKP symbols;
- and the first command is asserted when the descrambling circuit receives the COM symbol, and the second command is asserted when the descrambling circuit receives the SKP symbol.
Dependencies are inferred from the claim text.