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US 7,613,948 B2Granted
Cache coherency during resynchronization of self-correcting computer
AssigneeMaxwell Technologies, Inc.
InventorsRobert A. Hillman, Mark Steven Conrad
Life of this patent
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AssigneeMaxwell Technologies, Inc.
InventorsRobert A. Hillman, Mark Steven Conrad
Estimating the term…
A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled.
The method of operating a fault-tolerant computer system with at least three processors, comprising steps of:
A method of using a fault-tolerant computer system comprising at least three processors operating synchronously in parallel, wherein each processorr of the at least three processors comprise a memory management unit (MMU), the method comprising:
A method of operating a fault-tolerant computer system comprising a plurality of processors operating in lock-step, the method comprising:
Dependencies are inferred from the claim text.