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US 7,613,928 B2Granted
Flash device security method utilizing a check register
AssigneeMicron Technology, P.A.
InventorRobert Gentile
Life of this patent
Estimating the term…
Abstract
A security method for preventing accidental or unauthorized writes to a flash memory. According to one embodiment of the present invention, a BIOS program stored in a flash memory array generates a random access code when executed by a processor. A check register stores the random access code and enables write operations to the flash memory array based upon an externally provided access code. In another embodiment, the BIOS program directs the processor to write the random access code to the check register to enable write operations in response to an external write request.
Claims22
A flash memory system comprising:
- a memory array that contains a set of instructions adapted to cause an external device to initiate the creation of an access code by executing the set of instructions at the external device;
- and
- a check register to store the access code from the external device, wherein the check register generates a write enable signal to the memory array in response to receiving the access code, wherein the check register comprises:
- a compare register to store codes;
- an access code register to store the access code from the external device;
- and
- a register control circuit to compare a code stored in the compare register to the access code, wherein the register control circuit generates the write enable signal when a code written to the compare register matches the access code.
4 more elements
A flash memory system comprising:
- a memory array that contains a set of instructions adapted to cause an external device to initiate the creation of an access code by executing the set of instructions at the external device;
- and
- a check register to store the access code from the external device, wherein the check register generates a write enable signal to the memory array in response to receiving the access code;
- wherein the check register is volatile so the access code is erased when power is removed from the check register.
1 more element
A flash memory system comprising:
- a memory array that contains a set of instructions adapted to cause an external device to initiate the creation of an access code;
- and
- a check register to store the access code from the external device, wherein the check register generates a write enable signal to the memory array in response to the access code;
- wherein the access code is randomly generated by a program executed by a processor.
1 more element
A flash memory system comprising:
- a flash memory array having a BIOS program stored therein, wherein the BIOS program contains a program to initiate an access code generation by a processor;
- and
- a check register to store the access code from the processor, wherein the check register generates a write enable signal to the flash memory array based upon a request code from the processor;
- wherein the BIOS program directs the processor to write the access code to the check register to enable write operations in response to an external write request containing the request code.
1 more element
A flash memory system comprising:
- a flash memory array having a BIOS program stored therein, wherein the BIOS program contains a program to initiate an access code generation by a processor;
- and
- a check register to store the access code from the processor, wherein the check register generates a write enable signal to the flash memory array based upon a request code from the processor;
- wherein the program to generate the access code is located in a portion of the flash memory array that is protected from being written over.
1 more element
A flash memory system comprising:
- a flash memory array having a BIOS program stored therein, wherein the BIOS program contains a program to initiate an access code generation by a processor;
- a check register to store the access code from the processor, wherein the check register generates a write enable signal to the flash memory array based upon a request code from the processor;
- wherein the cheek register comprises:
- a compare register to store codes;
- an access code register to store the access code;
- and
- a register control circuit to compare a code stored in the compare register to the access code, wherein the register control circuit generates a write enable signal when a code written to the compare register matches the access code.
4 more elements
A flash memory system comprising:
- a flash memory array having a BIOS program stored therein, wherein the BIOS program contains a program to initiate an access code generation by a processor;
- a check register to store the access code from the processor, wherein the cheek register generates a write enable signal to the flash memory array based upon a request code from the processor;
- wherein a flash utility program, coupled to the processor, requests the BIOS to write the access code to the check register.
A flash memory system comprising:
- a memory array having a BIOS program stored therein;
- control circuitry to control write operations to the memory array;
- a processor to execute the BIOS program;
- and
- a programmed logic device having a code register to store a random access code generated by the processor in response to instructions contained in the BIOS program, wherein the programmed logic device gates a write enable signal to the control circuitry in response to a comparison of the stored random access code and a request code from the processor.
2 more elements
A method for operating a flash memory device having a check register and a memory array, the method comprising:
- instructing an external device to generate a first access code at power up;
- receiving the access code for storage in the check register;
- and
- toggling a write enable signal to the memory array in response to a comparison of a second access code contained in a received write command and the first access code.
1 more element
A method for operating a memory system having a memory device and a processor, the method comprising:
- the memory device directing the processor to generate an enable code;
- the processor issuing a write command to the memory device, the write command comprising a request code;
- and
- comparing the request code to the enable code and generating or disabling a write enable signal to the memory device in response to the comparison.
1 more element
Dependencies are inferred from the claim text.