US 7,613,912 B2 · System and method for simulating hardware interrupts

Abstract

A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a known memory area. In one embodiment, the processor has at least two pipelines that need to be aligned so that certain instructions are scheduled for the first pipeline and other instructions are scheduled for the other. In this embodiment, the BISLED also serves the purpose of re-aligning the instruction stream so that instructions are placed in the correct pipeline based upon the function performed by the instruction.

Claims20

Dependent claims

A computer-implemented method comprising:

identifying a plurality of unused slots in a plurality of pipelines, wherein each of the pipelines include instructions that are scheduled to execute on a processor, wherein the processor does not have hardware interrupt capabilities;
inserting, in a plurality of the identified unused slots, a conditional branch instruction, wherein the conditional branch instruction, when executed, branches on external data;
executing the inserted conditional branch instructions, wherein a predetermined memory location is checked each time each of the inserted conditional branch instructions is executed;
in response to no data being present in the predetermined memory location, the processor takes no action;
and
in response to data being present in the predetermined memory location, the processor branches to a registered interrupt handler.

3 more elements

A information handling system comprising:

a plurality of heterogeneous processors included in a single silicon substrate, wherein a selected one of the processors includes a plurality of pipelines and the selected processor does not have hardware interrupt capabilities;
a common memory also included in the single silicon substrate, the common memory accessible by the heterogeneous processors using a common bus;
and
a software tool that inserts conditional branch instructions in the plurality of pipelines, wherein the software tool, when executed by at least one of the processors, performs steps that include:
identifying a plurality of unused slots in the plurality of pipelines, wherein each of the pipelines include instructions that are scheduled to execute on the selected processor;
inserting, in a plurality of the identified unused slots, a conditional branch instruction, wherein the conditional branch instruction, when executed, branches on external data;
executing the instructions including the inserted conditional branch instructions, wherein a predetermined memory location in the common memory is checked each time each of the inserted conditional branch instructions is executed;
in response to no data being present in the predetermined memory location, the selected processor takes no action;
and
in response to data being present in the predetermined memory location, the selected processor branches to a registered interrupt handler.

7 more elements

A computer program product stored on a computer storage media that includes computer instructions that, when executed by an information handling system, causes the information handling system to perform steps comprising:

identifying a plurality of unused slots in a plurality of pipelines, wherein each of the pipelines include instructions that are scheduled to execute on a processor, wherein the processor does not have hardware interrupt capabilities;
inserting, in a plurality of the identified unused slots, a conditional branch instruction, wherein the conditional branch instruction, when executed, branches on external data;
executing the inserted conditional branch instructions, wherein a predetermined memory location is checked each time each of the inserted conditional branch instructions is executed;
in response to no data being present in the predetermined memory location, the processor takes no action;
and
in response to data being present in the predetermined memory location, the processor branches to a registered interrupt handler.

3 more elements

Dependencies are inferred from the claim text.

System and method for simulating hardware interrupts

Life of this patent

System and method for simulating hardware interrupts

Life of this patent

Abstract

Claims20