Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor

A method of scheduling threads in a processor having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising an execution unit and a thread scheduler, the method comprising:

• operating the execution unit to execute instructions in dependence on a first timing signal and to transfer data between the internal circuitry and the at least one port in dependence on the first timing signal;
• operating the thread scheduler to schedule a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the scheduling being in dependence on the first timing signal;
• transferring data between the at least one port and circuitry external to the processor in dependence on a second timing signal;
• and
• altering a ready signal in dependence on said second timing signal to indicate a transfer of data with the external circuitry;
• wherein said scheduling comprises:
• starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the interior external circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal.

A mobile terminal having a mobile applications processor, at least one peripheral device, and an interface processor connected between the mobile applications processor and the peripheral device, the interface processor having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising:

• an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the internal circuitry and the at least one port in dependence on the first timing signal;
• and
• a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal;
• wherein the at least one port is arranged to transfer data between the port and the mobile applications processor or peripheral device in dependence on a second timing signal, and to alter a ready signal in dependence on said second timing signal to indicate a transfer of data with the mobile applications processor or peripheral device;
• and
• the thread scheduler is configured such that said scheduling comprises:
• starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal.

An array of interconnected processors, at least one of said processors having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising:

• an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the internal circuitry and the at least one port in dependence on the first timing signal;
• and
• a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal;
• wherein the at least one port is arranged to transfer data between the port and another processor in the array in dependence on a second timing signal, and to alter a ready signal in dependence on said second timing signal to indicate a transfer of data with said other processor of the array;
• and
• the thread scheduler is configured such that said scheduling comprises:
• starting execution of said one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal.

A processor having an interface means and internal circuitry, the interface means comprising port means and the internal circuitry comprising:

• execution means for executing instructions in dependence on a first timing signal and for transferring data between the internal circuitry and the port means in dependence on the first timing signal;
• and
• thread scheduling means for scheduling a plurality of threads for execution by the execution means, each thread comprising a sequence of instructions and the scheduling by the thread scheduling means being in dependence on the first timing signal;
• wherein the port means are for transferring data between the port means and circuitry external to the processor in dependence on a second timing signal, and for altering a ready signal in dependence on said second timing signal to indicate a transfer of data with the external circuitry;
• and
• the thread scheduling means is for scheduling by:
• starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the port means and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal.

A computer program product for scheduling threads in a processor having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising an execution unit and a thread scheduler, comprising a storage media and a computer executable program wherein the program comprising code which when executed by a computer performs the steps of:

• transferring data between the internal circuitry and the at least one port in dependence on the first timing signal;
• operating the thread scheduler to schedule a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the scheduling being in dependence on the first timing signal;
• transferring data between the at least one port and circuitry external to the processor in dependence on a second timing signal;
• and
• altering a ready signal in dependence on said second timing signal to indicate a transfer of data with the external circuitry;
• wherein said scheduling comprises:
• starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal.