Data processing device with instruction translator and memory interface device to translate non-native instructions into native instructions for processor

A memory interface device with instruction translator to be arranged between a processor core and an external memory mapped into a predetermined external memory space, comprising:

• a fetch circuit for receiving an address value for access to said external memory space from said processor core, and fetching information at said address in said external memory, said information being an instruction nonnative to said processor, an instruction native to said processor, or data to be processed;
• a translator for translating the instruction nonnative to said processor core fetched by said fetch circuit from said external memory into the instruction native to said processor;
• and
• a select circuit for selectively applying the information read from said external memory space and the instruction prepared by translating the instruction read from said external memory space by said translator to said processor core depending on whether the address value for the access from said processor core to said external memory space is in a predetermined region or not, wherein
• a bus width of an instruction bus in said processor core is different from a bus width of a data bus of said external memory;
• and
• said select circuit includes;
• a bus width changing circuit having an input connected to said external memory and an output of a same width as the bus width of the instruction bus of said processor, for performing conversion between the bus width of the data bus of said external memory and the bus width of the instruction bus in said processor, and outputting a result, and
• a multiplexer having inputs connected to the outputs of said bus width changing circuit and said translator, respectively, and an output connected to said instruction bus of said processor core for selectively applying to said processor core an instruction output from said bus width changing circuit and an instruction output from said translator depending on whether the address value for the access from said processor core to said external memory space is within a predetermined region or not.

A data reading method for reading information from an external memory mapped into a predetermined external memory space to a processor core, comprising the steps of:

• receiving an address value for access from said processor core to said external memory space, and fetching the information at said address in said external memory, said data being an instruction nonnative to said processor, an instruction native to said processor, or data to be processed;
• translating the instruction normative to said processor core fetched from said external memory into the instruction native to the processor;
• and
• selectively applying the information read from said external memory space and the instruction prepared by the translation of the instruction read from said external memory space to said processor core depending on whether the address value for the access from said processor core to said external memory space is in a predetermined region or not, wherein
• a bus width of an instruction bus in said processor core is different from a bus width of a data bus of said external memory;
• and
• said selectively applying step includes the steps of:
• changing the data width of a fetched information by said external memory to the bus width of the instruction bus within said processor core, and
• selectively applying to said processor core the information having the changed bus width and the translated native instruction depending on whether the address value for the access from said processor core to said external memory space is within a predetermined region or not.