Output buffer circuit capable of synchronous and asynchronous data buffering using sensing circuit, and method and system of same

An output buffer circuit including first and second complementary inputs adapted to receive first and second complementary input signals, respectively, and including a clock input adapted to receive a clock signal, the output buffer operable in a synchronous mode of operation to store each of the first and second complementary input signals responsive to the clock signal and to provide the stored signals on first and second complementary outputs, respectively, and the output buffer operable in an asynchronous mode of operation to store each of the first and second complementary input signals responsive to a transition on each of the first and second complementary input signals and to provide the stored signals on the first and second complementary outputs, respectively.

An integrated circuit, comprising:

• electronic circuitry including an output buffer coupled to a first and second complementary outputs, the output buffer including,
• first and second complementary inputs adapted to receive first and second complementary input signals, respectively, and including a clock input adapted to receive a clock signal, the output buffer operable in a synchronous mode of operation to store each of the first and second complementary input signals responsive to the clock signal and to provide the stored signals on the first and second complementary outputs, respectively, and the output buffer operable in an asynchronous mode of operation to store each of the first and second complementary input signals responsive to a transition on each of the first and second complementary input signals and to provide the stored signals on the first and second complementary outputs, respectively.

A system, comprising:

• an electronic subsystem including electronic circuitry, the electronic circuitry including an output buffer coupled to first and second complementary outputs, the output buffer including,
• first and second complementary inputs adapted to receive first and second complementary input signals, respectively, and including a clock input adapted to receive a clock signal, the output buffer operable in a synchronous mode of operation to store each of the first and second complementary input signals responsive to the clock signal and to provide the stored signals on the first and second complementary outputs, respectively, and the output buffer operable in an asynchronous mode of operation to store each of the first and second complementary input signals responsive to a transition on each of the first and second complementary input signals and to provide the stored signals on the first and second complementary outputs, respectively.