US 7,613,760 B1 · Efficient implementation of multi-channel integrators and differentiators in a programmable device

Abstract

Efficiently implemented multi-channel integrators and multi-channel differentiators utilize a delay section in a single integrator or differentiator in lieu of parallel integrator or differentiator lines to handle multi-channel data flow and processing. The delay section functions like a shift register, greatly reducing the space and/or resources required for implementing the integrator or differentiator. Such integrators and differentiators can be used in multi-channel decimators, interpolators and numerically controlled oscillators in place of multiple instances of single channel integrators that have had to be used in earlier systems. These structures and devices can be implemented in programmable devices such as PLDs and similar devices, in which the delay section can be implemented in embedded memory in the device. Multi-stage decimators and interpolators can use multiple instances of an integrator and/or differentiator in series.

Claims30

Dependent claims

A multi-channel integrator comprising:

an integrator input;
an integrator output;
an adder comprising:
a first adder input connected to the integrator input;
a second adder input;
and
an adder output;
a delay section comprising:
a delay section input that receives data of a plurality of channels;
a delay section output;
and
a plurality of delay elements connected in series between the delay section input and the delay section output, each delay element of the plurality of delay elements delaying the data of each of the plurality of channels and providing an output that is specific to an individual channel of the plurality of channels;
and
a feedback line connecting the delay section output to the second adder input;
wherein the adder output is connected to the delay section input;
and
further wherein the delay section output is connected to the integrator output.

14 more elements

An N stage, M channel decimator, where M>1, the decimator comprising:

an integrator section comprising:
an integrator section input comprising a multiplexer comprising M multiplexer inputs and a multiplexer output;
an integrator section output;
and
N integrators connected in series between the integrator section input and the integrator output, wherein each integrator comprises:
an integrator input;
an integrator output;
an adder comprising:
a first adder input connected to the integrator input;
a second adder input;
and
an adder output;
a delay section comprising:
a delay section input;
a delay section output;
and M delay elements connected in series between the delay section input and the delay section output, each of the M delay elements delaying data of each of the M multiplexer inputs and providing an output that is specific to an individual channel of the M channels;
and
a feedback line connecting the delay section output to the second adder input;
wherein the adder output is connected to the delay section input;
and
further wherein the delay section output is connected to the integrator output;
a differentiator section comprising:
a differentiator section input;
a differentiator output;
and
N differentiators connected in series between the differentiator input and the differentiator output, wherein each differentiator comprises:
a differentiator input;
a differentiator output:
a subtractor comprising:
a first subtractor input;
a second subtractor input;
and
a subtractor output;
a delay section comprising:
a delay section input connected to the differentiator input;
a delay section output;
and
M delay elements connected in series between the delay section input and the delay section output;
and
a feedforward line connecting the differentiator input to the first subtractor input;
wherein the delay section output is connected to the second subtractor input;
and
wherein the subtractor output is connected to the differentiator output;
and
a down-sampler comprising a down-sampler input connected to the integrator section output and a down-sampler output connected to the differentiator section input.

42 more elements

An N stage, M channel interpolator, where M>1, the interpolator comprising:

a differentiator section comprising:
a differentiator section input comprising a multiplexer comprising M multiplexer inputs and a multiplexer output;
a differentiator output;
and
N differentiators connected in series between the differentiator input and the differentiator output, wherein each differentiator comprises:
a differentiator input;
a differentiator output:
a subtractor comprising:
a first subtractor input;
a second subtractor input;
and
a subtractor output;
a delay section comprising:
a delay section input connected to the differentiator input;
a delay section output;
and
M delay elements connected in series between the delay section input and the delay section output, each of the M delay elements delaying data of each of the M multiplexer inputs and providing an output that is specific to an individual channel of the M channels;
and
a feedforward line connecting the differentiator input to the first subtractor input;
wherein the delay section output is connected to the second subtractor input;
and
wherein the subtractor output is connected to the differentiator output;
an integrator section comprising:
an integrator section input;
an integrator section output;
and
N integrators connected in series between the integrator section input and the integrator output, wherein each integrator comprises:
an integrator input;
an integrator output;
an adder comprising:
a first adder input connected to the integrator input;
a second adder input;
and
an adder output;
a delay section comprising:
a delay section input;
a delay section output;
and
M delay elements connected in series between the delay section input and the delay section output;
and
a feedback line connecting the delay section output to the second adder input;
wherein the adder output is connected to the delay section input;
and
further wherein the delay section output is connected to the integrator output;
and
an up-sampler comprising an up-sampler input connected to the differentiator section output and an up-sampler output connected to the integrator section input.

43 more elements

Dependencies are inferred from the claim text.

Efficient implementation of multi-channel integrators and differentiators in a programmable device

Life of this patent

Efficient implementation of multi-channel integrators and differentiators in a programmable device

Life of this patent

Abstract

Claims30