Transceiver module and integrated circuit with dual eye openers and integrated loopback and bit error rate testing

An integrated circuit for use in a transceiver module, the integrated circuit comprising:

• a first electrical input port for receiving a first serial electrical data stream;
• receiver eye opener circuitry including components for retiming and reshaping the first serial electrical data stream, the components including a clock and data recovery, an equalizer, and a coefficient module, wherein the equalizer used a clock from the clock and data recovery and coefficients generated by the coefficient module to condition the first serial electrical data stream;
• a first electrical output port for transmitting the retimed and reshaped first serial electrical data stream to external to the integrated circuit;
• a second electrical input port for receiving a second serial electrical data stream from external to the integrated circuit;
• transmitter eye opener circuitry including components for retiming and reshaping the second serial electrical data stream;
• a second electrical output port for transmitting the retimed and reshaped second serial electrical data stream;
• and
• a bit error rate tester (BERT) engine for testing a test data path from a starting test point to an ending test point, the starting test point and the ending test point each located on either a receive path or on a transmit path, wherein the receive path is from the first electrical input port through the receiver eye opener circuitry to the first electrical output port and the transmit path is from the second electrical input port through the transmitter eye opener circuitry to the second electrical output port.