US 7,613,213 B2 · Time multiplexed SONET line processing

Abstract

Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.

Claims21

Dependent claims

A method for processing n number of SONET STS streams, where n is an integer greater than two, comprising:

deserializing each of the n number of streams;
buffering each deserialized stream;
generating a time wheel clock having a frequency greater than the aggregate deserialized data rate;
generating a plurality of clock signals synchronous to the time wheel clock, the plurality of signals each representing a plurality of time slots that include time slots corresponding to the n number of streams as well as a number of spare time slots;
utilizing at least one of the clock signals to multiplex the n streams over a parallel databus during the time slots corresponding to the n streams and generate a control signal that no valid data is present on the parallel databus during the spare time slots;
and
processing the multiplexed n streams in a pipeline, wherein the pipeline includes a plurality of shared circuits operating at the time wheel clock frequency.

4 more elements

An apparatus for processing n number of SONET STS streams, where n is an integer greater than two, comprising:

a multi-stream processing apparatus which includes
n number of serial to parallel converters having outputs outputting n number of byte wide data streams, said data streams having an aggregate data rate;
n number of buffers, each coupled to a respective output of a serial to parallel converter, said buffers having outputs outputting n number of buffered data streams;
a multiplexer coupled to said outputs of said n number of buffers, said multiplexer having an output outputting byte wide multiplexed data;
a byte-wide parallel data bus coupled to the output of said multiplexer;
a pipeline of processing circuits coupled to said data bus;
a time wheel clock generator generating a time wheel clock having a frequency greater than the aggregate data rate;
and
a clock signal generator generating a plurality of clock signals synchronous to the time wheel clock, the plurality of signals each representing a plurality of time slots that include time slots corresponding to the n number of data streams as well as a number of spare time slots, wherein the buffers utilize at least one of the clock signals to output the buffered data streams to the multiplexer for multiplexing the n streams over the byte-wide parallel data bus during the time slots corresponding to the n data streams, and a data valid generator utilizes at least one of the clock signals to generate a control signal that no valid data is present on the byte-wide parallel data bus during the spare time slots;
and
said time wheel clock is supplied to said pipeline of processing circuits.

8 more elements

Dependencies are inferred from the claim text.

Time multiplexed SONET line processing

Life of this patent

Time multiplexed SONET line processing

Life of this patent

Abstract

Claims21