US 7,613,211 B1Granted

Digital clock smoothing apparatus and method

AssigneeWideband Semiconductors, Inc.

InventorsRichard John Fagerlund, James P. Flynn, Mark Fong, David Bruce Isaksen

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Abstract

A method for digital clock smoothing comprising: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a two-port memory block; (B) accumulating a plurality of symbols of the asynchronous data stream in the two-port memory block for a predetermined time period; (C) computing an average symbol rate for the input asynchronous data stream; (D) generating a clock error signal equal to the difference between the average symbol rate of the input asynchronous data stream and a nominal output synchronous clock; (E) obtaining a smoothed symbol rate clock by using the error clock signal; and (F) generating an output smoothed data stream having the smoothed symbol rate clock.

Claims15

Dependent claims

A method for digital clock smoothing comprising:

(A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block;
(B1) obtaining said FIFO depth B by subtracting modulo B for each said stored symbol said symbol output address from said symbol input address;
(B2) inputting said FIFO depth B into a programmable LUT;
(B3) obtaining a phase detector error signal;
(B4) scaling said phase detector error signal to obtain a scaled error factor, wherein said scaled error factor is normalized by using a set of parameters selected from the group consisting of:
{a ratio of said input symbol rate to said reference clock;
and a damping factor configured to compensate for latency of said frequency lock loop (FLL)};
(B5) adding said scaled error factor to a nominal phase step to obtain a phase update;
(C) obtaining a smoothed symbol rate;
and
(D) reading out each output symbol from said FIFO under control of an output FIFO address control register at said smoothed symbol rate.

8 more elements

An apparatus for digital clock smoothing comprising:

(A1) a FIFO means configured to input said asynchronous data stream having an asynchronous symbol rate;
(B1) a means for obtaining said FIFO depth B by subtracting modulo B for each said stored symbol said symbol output address from said symbol input address;
(B2) a programmable LUT configured to input said FIFO depth B;
(B3) a phase detector configured to obtain a phase detector error signal;
(B4) a means for scaling said phase detector error signal to obtain a scaled error factor, wherein said scaled error factor is normalized by using a set of parameters selected from the group consisting of:
{a ratio of said input symbol rate to said reference clock;
and a damping factor configured to compensate for latency of said frequency lock loop (FLL)};
(B5) a means for adding said scaled error factor to a nominal phase step to obtain a phase update;
(C) a means for obtaining a smoothed symbol rate;
and
(D) a means for outputting each symbol at said smoothed symbol rate.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/357,685Filed 18 Feb 2006
Granted: 3 Nov 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 5/06
Methods or arrangements for data conversion without changing the order or content of the data handled: for changing the speed of data flow, i.e.…
G06F 2205/061
Indexing scheme relating to groups G06F5/06 - G06F5/16: adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or…
G06F
Computing and data processing

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