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US 7,613,208 B2Granted
Communication interface
AssigneeSTMicroelectronics S.r.l.
InventorsHerve Chalopin, Laurent Tabaries
Life of this patent
Estimating the term…
Abstract
An interface communicates between two communication buses which use at least two different protocols. The interface includes a volatile memory having at least two access ports and including two transcoding circuits, each transcoding circuit being specific to each of the protocols to be interfaced.
Claims16
A communication interface between a first and a second communication bus using respectively a first and a second protocol, each protocol having specifications suitable for the coding of data, said communication interface comprising:
- a memory comprising a first and a second access port, each of the ports being controllable independently of one another;
- a first transcoding circuit supporting the first protocol, and being coupled to the first access port of the memory, the first transcoding circuit making it possible to encode data situated in the memory so as to transmit them to the first bus according to the specifications of the first protocol, and/or making it possible to decode data received from the first bus according to the specifications of the first protocol so as to store them in the memory;
- a second transcoding circuit supporting the second protocol, and being coupled to the second access port of the memory, the second transcoding circuit making it possible to encode data situated in the memory so as to transmit them to the second bus according to the specifications of the second protocol, and/or making it possible to decode data received from the second bus according to the specifications of the second protocol so as to store them in the memory;
- and
- a control circuit coupled to the first and second transcoding circuits for ensuring synchronization between the transcoding circuits, so that the second transcoding circuit triggers the data encoding only after the first transcoding circuit has stored in the memory the data sufficient for a formatting according to the second protocol.
2 more elements
An integrated circuit, comprising:
- a communication interface between a first and a second communication bus using respectively a first and a second protocol, each protocol having specifications suitable for the formatting and packetizing of data, said communication interface including:
- a memory having a first and a second access port, each of the ports being controllable independently of one another;
- a first transcoding circuit supporting the first protocol, and being coupled to the first access port of the memory, the first transcoding circuit making it possible to encode data situated in the memory so as to transmit them to the first bus according to the specifications of the first protocol, and/or making it possible to decode data received from the first bus according to the specifications of the first protocol so as to store them in the memory;
- a second transcoding circuit supporting the second protocol, and being coupled to the second access port of the memory, the second transcoding circuit making it possible to encode data situated in the memory so as to transmit them to the second bus according to the specifications of the second protocol, and/or making it possible to decode data received from the second bus according to the specifications of the second protocol so as to store them in the memory;
- and
- a control circuit coupled to the first and second transcoding circuits for ensuring synchronization between the transcoding circuits, so that the second transcoding circuit triggers the data encoding only after the first transcoding circuit has stored in the memory the data sufficient for a formatting according to the second protocol.
3 more elements
A method of interfacing between a first and a second communication bus using respectively a first and a second communication protocol, each protocol having specifications suitable for data encoding, said method comprising the following steps of:
- receiving, by a first transcoding circuit supporting the first protocol, data originating from the first bus;
- decoding the data received, by the first transcoding circuit according to the specifications of the first protocol;
- storing the decoded data in a memory by way of a first port of the memory;
- reading the decoded data by a second transcoding circuit supporting the second protocol, the reading being performed by way of a second port of the memory;
- coding the data read according to the specifications of the second protocol, by the second transcoding circuit;
- and
- sending over the second bus the data formatted according to the second protocol,
- wherein a control circuit synchronizes the second transcoding circuit so that the second transcoding circuit triggers the coding step only after the first transcoding circuit has stored in the memory the data sufficient for a formatting according to the second protocol.
5 more elements
A communication interface between first and second communication buses respectively using first and second protocols, the communication interface comprising:
- a memory including first and second access ports, each of the ports being controllable independently of one another;
- a first transcoding circuit supporting the first protocol and being coupled to the first access port, the first transcoding circuit being structured to transcode data for transmission between the memory and the first communication bus;
- a second transcoding circuit supporting the second protocol, and being coupled to the second access port of the memory, the second transcoding circuit being structured to transcode data for transmission between the memory and the second communication bus;
- and
- a control circuit structured to synchronize the second transcoding circuit and trigger the second transcoding circuit to transcode the data only after the first transcoding circuit has stored in the memory the data sufficient for a formatting according to the second protocol.
2 more elements
Dependencies are inferred from the claim text.