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US 7,613,186 B2Granted
Processing multiplex sublayer data unit data in hardware
AssigneeVIA Telecom Co., Ltd.
InventorAlon Saado
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Abstract
The present invention concerns an apparatus comprising a data unit, a memory and a control unit. The data unit may be configured to generate an output signal comprising a series of frames each having a header and a payload in response to an input signal comprising a series of words. The memory may be configured to hold the output signal and to interface with a device. The control unit may be configured to present one or more control signals configured to control the data unit and the memory.
Claims21
An apparatus comprising:
- a data unit configured to (i) receive an input signal and a data valid signal, said input signal comprising a series of frames, each said frame having a header and a payload comprising a series of words, said data valid signal configured to indicate that said input signal is ready, and (ii) generate an output signal in response to a first word and a second word from said input signal, wherein said output signal comprises a third word comprising a number of bits selected from one or both of the first and the second words in response to a first control signal, and wherein the number of bits and position of the bits in the third word are (i) configured to be varied according to a current format of said frames and (ii) arranged in one of a plurality of formats based upon a second control signal;
- a memory configured to (a) store said output signal in response to one or more memory control signals and (b) provide an interface between said data unit and a device;
- and
- a control unit configured to generate (i) said first control signal, (ii) said second control signal, (iii) a third control signal presented to said data unit and (iv) said one or more memory control signals to control said memory all in response to both a start of frame signal and said data valid signal.
1 more element
A method for processing data comprising the steps of:
- (A) receiving an input signal and a data valid signal at a data unit circuit, said input signal comprising a series of frames, each said frame having a header and a payload comprising a series of words, said data valid signal being configured to indicate that said input signal is ready, and generating an output signal in response to a first word and a second word from the input signal, wherein said output signal comprises a third word comprising a number of bits selected from one or both of said first and said second words in response to a first control signal, and wherein the number of bits and position of the bits in said third word are (i) configured to be varied according to a current format of said frames and (ii) arranged in one of a plurality of formats based upon a second control signal;
- (B) storing said output signal in a memory in response to one or more memory control signals, wherein said memory provides an interface between said data unit circuit and a device;
- and
- (C) generating (i) said first control signal, (ii) said second control signal, (iii) a third control signal provided to said data unit circuit and (iv) said one or more memory control signals all in response to both a start of frame signal and said data valid signal.
1 more element
Dependencies are inferred from the claim text.