Method and apparatus for generating and distributing an internal clock for radio network controller

A method for generating an internal clock in a radio network controller, comprising:

• extracting, on a master transmission processing board, a clock signal from a synchronous/asynchronous line connected with a core network;
• generating, on said master transmission processing board, a reference transmission clock based on said clock signal extracted from the said synchronous/asynchronous line;
• and
• transmitting said reference transmission clock to a clock bus of a sub-rack in which said master transmission processing board is located
• in case of said master transmission processing board cannot extract the clock signal from said synchronous/asynchronous line, an Operation & Maintenance center in said radio network controller selecting a slave transmission processing board connected with said core network to function as a master transmission processing board.

A method for generating an internal clock in a radio network controller, comprising:

• generating, on a specified transmission processing board, a reference transmission clock;
• counting, on said specified transmission processing board, said reference transmission clock to generate a radio clock;
• broadcasting periodically said radio clock from said specified transmission processing board to at least one radio processing board in said radio network controller,
• wherein said generating the reference transmission clock further comprises:
• extracting a clock signal from a synchronous/asynchronous line connected with the core network on said specified transmission processing board;
• generating said reference transmission clock on said specified transmission processing board based on the clock signal extracted from said synchronous/asynchronous line.

A transmission processing board for a radio network controller, comprising:

• a clock signal selector for extracting a clock signal from a synchronous/asynchronous line connected with a core network when said transmission processing board functions as a master transmission processing board, and for obtaining a clock signal from a clock bus of a sub-rack in which said transmission processing board is located when said transmission processing board functions as a slave transmission processing board;
• a phase-locked loop for generating a reference transmission clock based on the clock signal extracted or obtained by said clock signal selector;
• and
• a clock driver for transmitting the generated reference transmission clock to the clock bus of the sub-rack in which said transmission processing board is located when said transmission processing board functions as a master transmission processing board.