Interleaved input signal path for multiplexed input
AssigneeMicron Technology, Inc.
InventorChang Wan Ha
Life of this patent
Estimating the term…
Abstract
System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner. In another embodiment, the command path includes a plurality of command latches that latch commands from the input signals in an interleaved manner and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner.
Claims21
A memory device comprising:
- an input node configured to receive command and address signals;
- a first latch coupled to the input node, the first latch configured to latch command signals responsive to a command latch signal;
- a second latch coupled to the input node, the second latch configured to latch address signals responsive to a first address latch signal;
- a third latch coupled to the input node, the third latch configured to latch address signals responsive to a second address latch signal;
- and
- clock logic coupled to the first, second, and third latches, the clock logic configured to receive a write enable signal and generate the command latch signal responsive to a first rising edge of the write enable signal, generate the first address latch signal responsive to a second rising edge of the write enable signal and the second address latch signal responsive to a third rising edge of the write enable signal.
A method for latching signals in a memory device, the method comprising:
- latching data from an input node to a first latch responsive to a command indication signal and a first rising edge of a write enable signal;
- latching data from the input node to a second latch responsive to an address indication signal and a second rising edge of the write enable signal;
- and
- latching data from the input node to a third latch responsive to the address indication signal and a third rising edge of the write enable signal.
A method for controlling a memory device having an internal time for processing a latched signal, the method comprising:
- coupling a command indication signal to the memory device;
- coupling a write enable signal to the memory device, the write enable signal having a plurality of rising edges;
- coupling a command signal to an input node of the memory device, the memory device configured to latch the command signal responsive to the command indication signal and a first rising edge of the write enable signal;
- coupling an address indication signal to the memory device;
- coupling a first address signal to the input node of the memory device, the memory device configured to latch the first address signal responsive to the address indication signal and a second rising edge of the write enable signal;
- and
- coupling a second address signal to the input node of the memory device, the memory device configured to latch the second address signal responsive to the address indication signal and a third rising edge of the write enable signal, a time between the second and third rising edges being less than the internal time for processing a latched signal of the memory device.
Dependencies are inferred from the claim text.