Semiconductor memory device
AssigneeElpida Memory, Inc.
InventorsSumio Ogawa, Yasuji Koshikawa
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
Claims22
A method of replacing a defect memory cell with a redundant memory cell in a semiconductor memory device which includes a plurality of memory blocks each having a plurality of segments each containing a plurality of memory cells and a plurality of redundant memory blocks each provided for an associated one of the plurality of memory blocks, the method comprising:
- storing redundant information indicative of segments having defect cells among the plurality of segments in a memory block among the plurality of memory blocks, wherein data cannot be read from or written to said defect cells;
- sequentially allocating the segments having defect cells to selected ones of the redundant memory blocks;
- and
- replacing the segments having defect cells with the selected ones of the redundant memory blocks, respectively,
- wherein said replacing comprises reading said data from or writing said data to the selected ones of said redundant memory blocks.
A method of replacing a defect memory cell with a redundant memory cell in a semiconductor memory device which includes a plurality of memory blocks and a plurality of redundant memory blocks each provided for an associated one of the plurality of memory blocks, each of the plurality of memory blocks having a plurality of segments, and each of the plurality of segments containing a plurality of memory cells, the method comprising:
- identifying plural segments each having one or more defect cells among the plurality of segments in a memory block among the plurality of memory blocks, wherein data cannot be read from or written to said defect cells;
- sequentially allocating a first one of the plural segments to one of the redundant memory blocks, which belongs to the memory block that includes the plural segments, and a second one of the plural segments to another of the redundant memory blocks, which belongs to the memory block that does not includes the plural segments;
- and
- replacing the plural segments by the one and another of the redundant memory blocks, respectively,
- wherein said replacing comprises reading said data from or writing said data to the one or another of said redundant memory blocks.
A method of replacing a defect memory cell with a redundant memory cell in a semiconductor memory device that includes a plurality of memory banks each including a plurality of normal memory blocks, each of the normal memory blocks including a plurality of normal memory cells, the method comprising:
- providing a plurality of redundant memory blocks to the normal memory blocks in each of the memory banks, respectively, the redundant memory blocks being thereby equal in number to the normal memory blocks, each of the redundant memory blocks including a plurality of redundant memory cells;
- storing a plurality of redundant information each indicative of a defect memory cell among the normal memory cells, the plurality of redundant information including first and second redundant information indicating respectively first and second normal memory cells among the normal memory cells each belonging to one of the normal memory blocks, the one of the normal memory blocks thereby including the first and second normal memory cells;
- and
- replacing the first normal memory cell indicated by the first redundant information with one of the redundant memory cells each belonging to a first one of the redundant memory blocks and the second normal memory cell indicated by the second redundant information with one of the redundant memory cells each belonging to a second one of the redundant memory blocks, which is different from the first one of the redundant memory blocks.
A method of replacing a defective memory cell with a redundant memory cell in a semiconductor memory device that includes a plurality of memory banks each including a plurality of normal memory blocks and a plurality of redundant memory blocks, each of the normal memory blocks including a plurality of normal memory cells, each of the redundant memory blocks including a plurality of redundant memory cells, the method comprising:
- storing first redundant information associating a first defective normal memory cell among the normal memory cells with a first redundant memory cell among the redundant memory cells;
- storing second redundant information associating a second defective normal memory cell among the normal memory cells with a second redundant memory cell among the redundant memory cells, each of said first and second normal memory cells belonging to one of the normal memory blocks;
- replacing the first defective normal memory cell with the first redundant memory cell which belongs to a first one of the redundant memory blocks;
- and
- replacing the second defective normal memory cell with the second redundant memory cell which belongs to a second one of the redundant memory blocks which is different from the first one of the redundant memory blocks.
A method of replacing a defective memory cell with a redundant memory cell in a semiconductor memory device that includes at least first and second memory banks, the first memory bank including a plurality of first memory blocks, each of the first memory blocks including a plurality of normal memory cells and a plurality of redundant memory cells, the second memory bank including a plurality of second memory blocks, each of the second memory blocks including a plurality of normal memory cells and a plurality of redundant memory cells, the method comprising:
- storing first defective address information indicative of a first defective normal memory cell among the normal memory cells in the first memory bank;
- storing second defective address information indicative of a second defective normal memory cell among the normal memory cells in the first memory bank, the first and second defective normal memory cells belonging to one of the first memory blocks in the first memory bank;
- replacing, in response to the first defective address information, the first defective normal memory cell with a first redundant memory cell which belongs to a first one of the first memory blocks in the first memory bank;
- and
- replacing, in response to the second defective address information, the second defective normal memory cell with a second redundant memory cell which belongs to a second one of the first memory blocks in the first memory bank which is different from the first one of the first memory blocks in the first memory bank.
Dependencies are inferred from the claim text.