Sense-amplifier assist (SAA) with power-reduction technique

A design structure instantiated in a machine readable medium for designing or manufacturing a sense amplifier circuit, the design structure, comprising:

• a pair of p-channel transistors;
• a first pair of n-channel transistors;
• an n-channel transistor coupled to a common node between the first pair of n-channel transistors;
• a second pair of n-channel transistors with common drain and ground connections;
• a bit switch circuit;
• and
• a global bit-line circuit,
• wherein the pair of p-channel transistors are cross-coupled,
• wherein the first pair of n-channel transistors are cross-coupled and the first pair of n-channel transistors and the pair of p-channel transistors are both further coupled to a complementary pair of bit-lines,
• wherein a gate of the n-channel transistor is configured to receive an input signal for setting the sense amplifier,
• wherein a gate of the first n-channel transistor of the second pair of n-channel transistors is configured to receive a mask input signal for masking unselected bit-lines,
• wherein a gate of the second n-channel transistor of the second pair of n-channel transistors is coupled to the bit switch,
• wherein the bit switch is coupled to a global bit-line circuit,
• wherein the design structure comprises a netlist that describes the sense amplifier circuit,
• and wherein the mask input signal is set to VDD, the bit-lines in a subarray is set by a global set signal.