Decoding system capable of reducing sector select area overhead for flash memory
AssigneeSpansion LLC
InventorsJiani Zhang, Nian Yang, Aaron Lee
Life of this patent
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Abstract
Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods are disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits.
Claims19
A memory device, comprising:
- a physical sector comprising a plurality of core sectors organized in a virtual ground configuration;
- wherein the plurality of core sectors comprise:
- a plurality of memory cells;
- a plurality of gate terminals coupled to at least one wordline;
- a plurality of drain terminals coupled to at least one bitline;
- a plurality of source terminals coupled to at least one bitline;
- a decoder operatively coupled to the at least one wordline of the plurality of core sectors;
- and
- wherein the decoder comprises a shifter, an x-dec circuit, and at least one x-dec sub circuit;
- wherein the decoder is configured to maintain isolated control of the at least one wordline of the plurality of core sectors and further configured to inhibit at least one core sector by generating an inhibiting voltage to the at least one core sector within the physical sector.
A method of manufacturing a memory device, comprising:
- forming a physical sector comprising a plurality of core sectors;
- wherein each core sector comprises:
- a plurality of memory cells;
- a plurality of gate terminals coupled to at least one wordline;
- a plurality of drain terminals coupled to at least one bitline;
- a plurality of source terminals coupled to at least one bitline;
- isolating control of at least one core sector within the physical sector;
- and
- generating an inhibiting voltage to at least one wordline of the plurality of core sectors within the physical sector by a decoder;
- wherein the decoder comprises a shifter, an x-dec circuit, and at least one x-dec sub circuit.
A communication device, comprising:
- a flash memory CPU;
- the flash memory operatively coupled to the CPU and configured to transfer data to and from the CPU;
- an input component for entering the data;
- a display component for displaying information;
- a plurality of switches;
- flash memory;
- a physical sector;
- and
- a method of forming a physical sector comprising a plurality of core sectors;
- wherein each core sector comprises:
- a plurality of memory cells;
- a plurality of gate terminals coupled to at least one wordline;
- a plurality of drain terminals coupled to at least one bitline;
- a plurality of source terminals coupled to at least one bitline;
- isolating control of at least one core sector within the physical sector;
- and
- generating an inhibiting voltage to at least one wordline of the plurality of core sectors within the physical sector by a decoder while concurrently generating an erase voltage to at least one wordline of the plurality of core sectors;
- wherein the decoder comprises:
- a row decoder
- a circuit for generating a high voltage signal;
- a sub circuit for passing a control signal for a negative voltage to be generated to at least one wordline of the plurality of core sectors or a positive voltage to at least one core sector of the plurality of core sectors;
- wherein generating the inhibiting voltage comprises generating a high positive voltage from a VWL node;
- and
- wherein generating the negative voltage comprises generating a high negative voltage from a minus voltage or a float;
- forming a column decoder comprising a sense amplifier and two sector select circuits coupled to and shared among the plurality of core sectors.
Dependencies are inferred from the claim text.