US 7,613,041 B2 · Methods for operating semiconductor device and semiconductor memory device

Abstract

Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the third conductive region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region. The present invention further provides an energy band engineering method permitting the devices be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Claims20

Dependent claims

A method of operating a semiconductor device having a strained tunneling gate, strained ballistic gate disposed adjacent to and insulated from the strained tunneling gate, a storage region disposed adjacent to and insulated from the strained ballistic gate, and a strain source providing a mechanical stress to the strained tunneling gate and the strained ballistic gate to provide a piezo-effect, the method comprising the steps of:

applying a first voltage to the strained tunneling gate;
applying a second voltage to the strained ballistic gate;
and
applying a third voltage to the storage region to inject charge carriers from the strained tunneling gate through the strained ballistic gate into the storage region.

1 more element

A method of operating a nonvolatile memory cell having a plurality of states, the memory cell comprising a strained tunneling gate, a strained ballistic gate disposed adjacent to and insulated from the strained tunneling gate, a storage region disposed adjacent to and insulated from the strained ballistic gate, a strain source providing a mechanical stress to the strained tunneling gate and the strained ballistic gate to provide a piezo-effect, and spaced-apart source and drain regions of a first conductivity type in a body of a semiconductor of a second conductivity type, the method comprising the steps of:

applying a first voltage to the strained tunneling gate;
applying a second voltage to the strained ballistic gate;
applying a body voltage to the body;
applying a source voltage to the source region;
and
applying a drain voltage to the drain region to establish one of the plurality of states of the memory cell by injecting charge carriers from the strained tunneling gate through the strained ballistic gate into the storage region.

3 more elements

Dependencies are inferred from the claim text.

Methods for operating semiconductor device and semiconductor memory device

Life of this patent

Methods for operating semiconductor device and semiconductor memory device

Life of this patent

Abstract

Claims20