Semiconductor memory device and control method thereof

A control method of a semiconductor memory device,

• the device comprising:
• a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter;
• a write word line and a read word line connected to the memory cells;
• and
• a plurality of first write bit lines, a plurality of second write bit lines and a plurality of read bit lines connected to the memory cells, respectively,
• each of the memory cells including:
• a first transfer gate which is connected between the first storage node and the corresponding first write bit line, and has a gate connected to the write word line;
• a second transfer gate which is connected between the second storage node and the corresponding second write bit line, and has a gate connected to the write word line;
• a drive transistor which has a gate connected to the first storage node, and a source connected to a power supply;
• and
• a third transfer gate which is connected between a drain of the drive transistor and the corresponding read bit line, and has a gate connected to the read word line,
• the method comprising:
• writing input data to a selected memory cell in write operation;
• and
• writing again data stored in a non-selected memory cell to the non-selected memory cell in the write operation.

A control method of a semiconductor memory device,

• the device comprising:
• a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter;
• a write word line and a read word line connected to the memory cells;
• and
• a plurality of first bit lines and a plurality of second bit lines connected to the memory cells, respectively,
• each of the memory cells including:
• a first transfer gate which is connected between the first storage node and the corresponding first bit line, and has a gate connected to the write word line;
• a second transfer gate which is connected between the second storage node and the corresponding second bit line, and has a gate connected to the write word line;
• a drive transistor which has a gate connected to the first storage node, and a source connected to a power supply;
• and
• a third transfer gate which is connected between a drain of the drive transistor and the corresponding second bit line, and has a gate connected to the read word line,
• the method comprising:
• writing input data to a selected memory cell in write operation;
• and
• writing again data stored in a non-selected memory cell to the non-selected memory cell in the write operation.