System, apparatus, and method to increase read and write stability of scaled SRAM memory cells

A static random access memory (SRAM), comprising:

• a plurality of memory cells wherein a stability of each memory cell is modifiable by adjusting a well bias signal operably coupled to a well containing at least one transistor for each memory cell;
• and
• at least one well bias driver for generating the well bias signal at:
• a supply voltage when the stability is within a predetermined range after testing;
• and
• a bias offset from the supply voltage when the stability is outside the predetermined range after testing.

A static random access memory (SRAM), comprising:

• a plurality of memory cells wherein a read stability and a write stability of each memory cell is modifiable by adjusting a well bias signal operably coupled to a well containing at least one transistor for each memory cell;
• and
• at least one well bias driver for generating the well bias signal at:
• for read operations, one of a supply voltage, a bias offset from the supply voltage, and a second bias offset from the supply voltage;
• and
• for write operations, one of the supply voltage, the bias offset from the supply voltage, and the second bias offset from the supply voltage.

A computing system, comprising:

• at least one processor;
• and
• at least one static random access memory (SRAM), comprising:
• a plurality of memory cells wherein a stability of each memory cell is modifiable by adjusting a well bias signal operably coupled to a well containing at least one transistor for each memory cell;
• and
• at least one well bias driver for generating the well bias signal;
• wherein the well bias signal is adjustable to:
• a supply voltage when the stability is tested to be within a predetermined range;
• and
• a bias offset from the supply voltage when the stability is tested to be outside the predetermined range.

A method of operating a memory device, comprising:

• operating a plurality of memory cells that each include at least one transistor in a well configured to be biased at a supply voltage or a bias offset from the supply voltage;
• determining whether the plurality of memory cells on the memory device operate correctly within predetermined parameters when biased at the supply voltage;
• operating the memory device with the well biased at the supply voltage if the memory device operates correctly within the predetermined parameters when biased at the supply voltage;
• and
• operating the memory device with the at least one N-well biased at the bias offset from the supply voltage if the memory device does not operate correctly within the predetermined parameters when biased at the supply voltage.

A method of adjusting a memory device, comprising:

• testing the memory device for stable read operations and stable write operations;
• and
• modifying a well bias to an adjusted well bias by:
• increasing the well bias to memory cells on the memory device if the memory device is not stable for the write operations;
• and
• decreasing the well bias to memory cells on the memory device if the memory device is not stable for the read operations.