Dram cell design with folded digitline architecture and angled active areas
AssigneeMicron Technology, Inc.
InventorsFei Wang, Anton P. Eppich
Life of this patent
Estimating the term…
Abstract
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6 F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3 F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.
Claims30
A DRAM device comprised of a plurality of memory cells having an effective size of 6 F2, comprising:
- a plurality of dual bit active areas, each of said active areas having a substantially longitudinal axis;
- and
- a plurality of digitlines arranged in a folded digitline architecture, wherein said digitlines have a 3 F pitch and 2 F space between adjacent digit lines, and wherein said active areas are positioned such that the longitudinal axis of said active areas is oriented at an angle with respect to a centerline of said digitlines.
A DRAM device comprised of a plurality of memory cells, comprising:
- a plurality of dual bit active areas, each of said active areas having a substantially longitudinal axis;
- a plurality of digitlines arranged in a folded digitline architecture, said active areas being positioned such that the longitudinal axis of said active areas is oriented at an angle with respect to a centerline of said digitlines;
- and
- a plurality of word lines having a pitch which is one third that of the digitlines.
A DRAM device comprised of a plurality of memory cells, comprising:
- a plurality of dual bit active areas, each of said active areas having a substantially longitudinal axis;
- a plurality of digitlines arranged in a folded digitline architecture, said active areas being positioned such that the longitudinal axis of said active areas is oriented at an angle with respect to a centerline of said digitlines;
- and
- a plurality of word lines, space between adjacent of the digitlines being four times space between adjacent of the word lines.
A DRAM device comprised of a plurality of memory cells, comprising:
- a plurality of dual bit active areas, each of said active areas having a substantially longitudinal axis;
- a plurality of digitlines arranged in a folded digitline architecture, said active areas being positioned such that the longitudinal axis of said active areas is oriented at an angle with respect to a centerline of said digitlines;
- and
- an elongated capacitor contact area within each of the active areas, said elongated capacitor contact area having opposing ends, one of the ends having a curved portion, another of the ends being void of any curved portion.
Dependencies are inferred from the claim text.